Self-Checking Testbenches

A self-checking testbench decides pass or fail on its own — no human reading waveforms. This is non-negotiable for regression: thousands of tests run nightly, and only a test that checks itself can flag a failure automatically. The rule is simple: every stimulus must have an automatic check against an independent expectation, and the test must end with an unambiguous PASS/FAIL.

Anatomy of a self-checking test

Generate stimulus, compute the expected result from a reference (not from the DUT), compare, count errors, and report. The example verifies an ALU against independent reference expressions across random vectors and exits with a clear verdict and a non-ambiguous error count:

module alu(input [7:0] a, b, input [1:0] op, output reg [8:0] y);
  always @(*) case(op)
    2'd0: y = a + b;
    2'd1: y = a - b;
    2'd2: y = a & b;
    default: y = a | b;
  endcase
endmodule

module tb;
  reg [7:0] a,b; reg [1:0] op; wire [8:0] y;
  integer i, errors=0; reg [8:0] exp;
  alu u(a,b,op,y);
  initial begin
    for (i=0;i<200;i=i+1) begin
      a=$random; b=$random; op=$random;
      #1;
      case(op)                               // independent reference
        2'd0: exp=a+b; 2'd1: exp=a-b; 2'd2: exp=a&b; default: exp=a|b;
      endcase
      if (y!==exp) begin errors=errors+1; $display("FAIL op=%0d a=%0d b=%0d got=%0d exp=%0d",op,a,b,y,exp); end
    end
    $display("ran 200 vectors: errors=%0d -> %s", errors, errors? "TEST FAILED":"TEST PASSED");
    $finish;
  end
endmodule
ran 200 vectors: errors=0 -> TEST PASSED

Check yourself

Why can’t a regression suite rely on an engineer inspecting waveforms?

Regressions run thousands of tests repeatedly and automatically; no human can review that volume, and bugs would slip through. Each test must check itself and emit a machine-readable PASS/FAIL so failures are caught and reported without manual inspection.

Where must the ‘expected’ value in a self-checking test come from?

From an independent reference (the spec, a golden model, or a separate expression) — never recomputed from the DUT’s own output. Otherwise a DUT bug would corrupt both the actual and expected value and the check would pass incorrectly.

Have questions about this topic?
Share your question in comments or talk to our mentor team for batch guidance.

Need Fee, Duration, or Demo Class Details?

Talk to our admin team for the latest batch plan and career guidance.

Contact Admin Team
▶ Try it in the ChipXpert Lab

Compile and simulate this in the browser — no install. Edit the code and re-run instantly.

Open in Verification Lab

Learn Verilog with mentors, labs and placement support

This free series is maintained by the ChipXpert training team in Hyderabad & Bengaluru. Go deeper with instructor-led courses on real EDA tools.

Explore VLSI Courses
Next batch starts 18th November 2026
Start your VLSI career with ChipXpert

Live online and classroom batches in Hyderabad & Bengaluru. Fill in your details and a counsellor will call you back.

  • Real EDA tools in your browser: industry-standard EDAReal EDA tools in your browser
  • Recorded sessions on the elearn portalRecorded sessions
  • Placement assistance: resume, mock interviewsPlacement assistance
  • Merit scholarship up to 60% · EMI optionsScholarship up to 60%
Hi! Ask me about courses, fees, batches or discounts. ×
BENGALURU
HYDERABAD