Verilog FSM Design: Moore, Mealy and the Three-Block Style

A finite state machine (FSM) is the backbone of control logic — protocol handlers, arbiters, bus controllers. This chapter is the design pattern; for a ready-to-copy design see FSM Verilog code examples.

Moore vs Mealy

In a Moore machine the output depends only on the current state — glitch-free and easy to reason about. In a Mealy machine the output also depends on the inputs, so it reacts one cycle sooner but can glitch. Default to Moore unless you need the earlier response.

The three-block style

The robust, synthesis-friendly template splits the FSM into three parts: a state register (sequential), next-state logic (combinational) and output logic (combinational). Here is a Moore sequence detector for the pattern 101:

module seq101 (input clk, rst, din, output reg found);
  localparam S0=2'd0, S1=2'd1, S10=2'd2, S101=2'd3;
  reg [1:0] state, nxt;

  // 1) state register (sequential, non-blocking)
  always @(posedge clk or posedge rst)
    if (rst) state <= S0; else state <= nxt;

  // 2) next-state logic (combinational, blocking)
  always @(*) case (state)
    S0:   nxt = din ? S1  : S0;
    S1:   nxt = din ? S1  : S10;
    S10:  nxt = din ? S101: S0;
    S101: nxt = din ? S1  : S10;
    default: nxt = S0;
  endcase

  // 3) output logic (Moore: depends on state only)
  always @(*) found = (state == S101);
endmodule

module tb;
  reg clk, rst, din; wire found;
  seq101 dut (.clk(clk), .rst(rst), .din(din), .found(found));
  always #5 clk = ~clk;
  // stream 1 1 0 1 0 1  -> "101" completes twice
  reg [5:0] stream = 6'b110101; integer i;
  initial begin
    clk=0; rst=1; din=0; #12 rst=0;
    for (i=5; i>=0; i=i-1) begin
      din = stream[i]; @(posedge clk);
      #1 $display("t=%0t din=%b state=%0d found=%b", $time, din, dut.state, found);
    end
    #5 $finish;
  end
endmodule

t=16 din=1 state=1 found=0
t=26 din=1 state=1 found=0
t=36 din=0 state=2 found=0
t=46 din=1 state=3 found=1
t=56 din=0 state=2 found=0
t=66 din=1 state=3 found=1

Note how the three blocks map exactly onto the rules from blocking vs non-blocking: the state register is clocked and uses <=; the two combinational blocks use =.

▶ Try it in the ChipXpert Lab

Drive the detector with a constrained-random bit stream and a scoreboard in the cocotb verification lab to prove it fires on every 101 — the kind of check EDA Playground can’t run.

Open the Verification Lab →

Check yourself

Why is the state register in its own always block with <code><=</code>?

It is the only sequential part of the FSM — it must update on the clock edge like a real register, so it uses non-blocking assignment. Keeping it separate from the combinational next-state and output logic is what makes the three-block style synthesise cleanly.

When would you pick a Mealy machine over Moore?

When you need the output to respond in the same cycle as the input rather than one cycle later. The cost is that Mealy outputs can glitch as inputs settle, so Moore is the safe default for most control logic.

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