Verilog Introduction: Modules, Nets and Modelling Styles

Verilog is a hardware description language (HDL). Unlike a software language, where statements run one after another on a CPU, Verilog describes hardware that exists all at once — gates, flip-flops and wires that are physically present and operate in parallel. Learning Verilog is mostly learning to think in terms of concurrent hardware rather than sequential instructions.

This series is the free reference companion to the instructor-led VLSI programs at ChipXpert. Every code example on every page is compiled and simulated with the open-source Icarus Verilog toolchain before it is published, so what you read is what actually runs.

The building block: a module

Every Verilog design is a hierarchy of modules. A module has a name, a list of ports (its connections to the outside world), and a body that describes its behaviour or structure. Here is a complete, self-contained example — a 2-input AND gate and a tiny testbench that drives it:

module and_gate (input a, input b, output y);
  assign y = a & b;   // continuous assignment: y always tracks a & b
endmodule

module tb;
  reg a, b;
  wire y;
  and_gate dut (.a(a), .b(b), .y(y));   // instantiate, connect by name
  initial begin
    a = 0; b = 0; #1 $display("a=%b b=%b -> y=%b", a, b, y);
    a = 1; b = 0; #1 $display("a=%b b=%b -> y=%b", a, b, y);
    a = 1; b = 1; #1 $display("a=%b b=%b -> y=%b", a, b, y);
    $finish;
  end
endmodule

a=0 b=0 -> y=0
a=1 b=0 -> y=0
a=1 b=1 -> y=1

Two ways to describe hardware

Verilog gives you three modelling styles, and real designs mix them:

• Dataflow — assign statements that describe combinational logic as expressions (the AND gate above).
• Behavioural — always and initial blocks that describe what happens, leaving the synthesiser to build the gates.
• Structural — instantiating and wiring sub-modules, the way the testbench instantiates and_gate.

Wires vs registers

Two net types trip up every beginner. A wire is driven continuously by something else (an assign or a module output). A reg holds its value until a procedural block changes it. A reg is not necessarily a hardware register — it is simply a variable that can be assigned inside always/initial. Use wire for the output of assign, and reg for anything you assign procedurally.

What to read next

Continue with Verilog data types to learn the full set of nets and variables, then operators and the procedural blocks that bring a design to life.