Verilog Tasks and Functions

As designs grow, you factor repeated behaviour into tasks and functions. They are Verilog’s subroutines — but the two differ in ways that matter for both simulation and synthesis.

functiontask
Time / delaysnone — executes in zero timemay contain #, @, wait
Returnsexactly one valuenone (use output args)
Callsonly other functionstasks or functions
Typical usecombinational helperstimulus / multi-step sequence

A function: pure, combinational, returns a value

module fn_demo;
  function [3:0] bcd_inc (input [3:0] d);   // returns one 4-bit value
    bcd_inc = (d == 4'd9) ? 4'd0 : d + 4'd1;
  endfunction

  integer i; reg [3:0] v;
  initial begin
    v = 4'd7;
    for (i = 0; i < 4; i = i + 1) begin
      $display("v=%0d", v);
      v = bcd_inc(v);                       // call like an expression
    end
    $finish;
  end
endmodule
v=7
v=8
v=9
v=0

A task: can consume time, drives outputs

module task_demo;
  reg clk; reg [7:0] bus;
  task send (input [7:0] data);             // multi-step, time-consuming
    begin
      @(posedge clk) bus = data;
      $display("t=%0t sent %0h", $time, bus);
    end
  endtask
  always #5 clk = ~clk;
  initial begin
    clk = 0; bus = 0;
    send(8'hA5);
    send(8'h3C);
    #3 $finish;
  end
endmodule
t=5 sent a5
t=15 sent 3c

Rule of thumb: if it needs a clock edge or a delay, it must be a task. If it is a one-shot combinational computation, make it a function — functions are synthesisable and keep combinational logic tidy.

▶ Try it in the ChipXpert Lab

Run both demos in the lab. Then try adding a #5 delay inside the function — the simulator will reject it, proving functions execute in zero time.

Open the Simulator →

Check yourself

Can a function contain <code>@(posedge clk)</code>?

No. Functions must execute in zero simulation time and cannot contain timing controls (#, @, wait). Anything that waits for an event must be a task.

How does a task return results if it has no return value?

Through output (and inout) arguments in its port list. A task can produce several results this way, whereas a function returns exactly one value as its name.

Have questions about this topic?
Share your question in comments or talk to our mentor team for batch guidance.

Learn Verilog with mentors, labs and placement support

This free series is maintained by the ChipXpert training team in Hyderabad & Bengaluru. Go deeper with instructor-led courses on real EDA tools.

Explore VLSI Courses
Next batch starts 18th November 2026
Start your VLSI career with ChipXpert

Live online and classroom batches in Hyderabad & Bengaluru. Fill in your details and a counsellor will call you back.

  • Real EDA tools in your browser: industry-standard EDAReal EDA tools in your browser
  • Recorded sessions on the elearn portalRecorded sessions
  • Placement assistance: resume, mock interviewsPlacement assistance
  • Merit scholarship up to 60% · EMI optionsScholarship up to 60%
Hi! Ask me about courses, fees, batches or discounts. ×
BENGALURU
HYDERABAD