Verilog Modules and Ports

A module is the unit of design and reuse in Verilog. Mastering its ports — how a module talks to the world and how you connect instances — is the foundation of every structural design.

Declaring ports

Ports have a direction (input, output, or bidirectional inout) and a width. The modern ANSI style declares type and direction together in the header:

module alu
  #(parameter WIDTH = 8)                 // parameter: width is configurable
  (input  [WIDTH-1:0] a, b,
   input  [1:0]       op,
   output reg [WIDTH-1:0] y,
   output             zero);             // 1-bit status flag

  assign zero = (y == 0);
  always @(*) case (op)
    2'b00: y = a + b;
    2'b01: y = a - b;
    2'b10: y = a & b;
    default: y = a | b;
  endcase
endmodule

module tb;
  reg [7:0] a,b; reg [1:0] op; wire [7:0] y; wire zero;
  alu #(.WIDTH(8)) dut (.a(a), .b(b), .op(op), .y(y), .zero(zero));
  initial begin
    a=8'd10; b=8'd10; op=2'b01; #1 $display("10-10 = %0d zero=%b", y, zero);
    a=8'd6;  b=8'd3;  op=2'b00; #1 $display("6+3  = %0d zero=%b", y, zero);
    a=8'hF0; b=8'h0F; op=2'b10; #1 $display("F0&0F= %0h", y);
    $finish;
  end
endmodule

10-10 = 0 zero=1
6+3  = 9 zero=0
F0&0F= 0

Connecting instances: named vs positional

Always connect ports by name (.a(a)), as above. Positional connection — listing signals in port order — is legal but fragile: reorder the ports and every instance silently mis-wires. Named connection is self-documenting and reorder-proof.

Parameters make modules reusable

The #(parameter WIDTH=8) lets one alu description serve any bus width. Override it per instance with #(.WIDTH(16)). See Verilog parameters for the full story.

▶ Try it in the ChipXpert Lab

Instantiate the ALU in the lab, change .WIDTH(8) to 16, widen the stimulus and re-simulate to see the parameter propagate.

Open the Simulator →

Check yourself

Why prefer named port connection over positional?

Named connection (.a(a)) binds each signal to a specific port, so adding or reordering ports cannot silently mis-wire an instance. Positional connection depends on the exact port order and breaks quietly when the module changes.

What is the difference between a parameter and an input?

A parameter is fixed at elaboration (compile) time and configures the hardware’s structure, such as bus width. An input is a runtime signal that changes during simulation. You override a parameter per instance; you drive an input with stimulus.

Have questions about this topic?
Share your question in comments or talk to our mentor team for batch guidance.

Learn Verilog with mentors, labs and placement support

This free series is maintained by the ChipXpert training team in Hyderabad & Bengaluru. Go deeper with instructor-led courses on real EDA tools.

Explore VLSI Courses