Top Verilog Interview Questions and Answers

Blocking assignments execute in order within a block, like software statements — the next line sees the updated value. Non-blocking assignments sample all right-hand sides first, then update together at the end of the time step, modelling flip-flops that clock simultaneously. Rule of thumb: use non-blocking in clocked (sequential) always blocks and blocking in combinational ones. Mixing them or using blocking for sequential logic causes simulation-synthesis mismatches and races.

wire models a physical net driven continuously (by assign or a module output); it cannot hold state. reg is a variable assigned inside procedural blocks (always/initial); despite the name it does not necessarily become a hardware register — whether it infers a flip-flop, latch or just combinational logic depends on how it is assigned.

An incompletely specified combinational always block — a case or if that doesn’t assign the output on every path — makes the tool infer a latch to ‘remember’ the missing case. Avoid it by assigning every output in every branch, using a default assignment at the top of the block, and including a default in case statements. SystemVerilog’s always_comb flags it at compile time.

== is logical equality and returns x if either operand contains x or z. === is case equality and compares x and z bits literally, returning a definite 0/1 — it is used in testbenches to check for exact x/z values. === is not synthesizable.

Because a loop with static bounds is unrolled at elaboration into parallel hardware — it is not a runtime loop. Each iteration becomes its own copy of the logic. Only loops whose bounds are known at compile time synthesize; data-dependent loop counts do not.

case matches exactly. casez treats z (and ?) bits as don’t-cares. casex treats both x and z as don’t-cares — which is dangerous in real hardware because an accidental x matches anything and can mask bugs, so casez (or SystemVerilog case inside) is preferred.

Synchronous: the reset is only in the sensitivity list’s clock edge — always @(posedge clk) if (rst) ...; it is sampled like data. Asynchronous: the reset edge is in the sensitivity list — always @(posedge clk or negedge rst_n) if (!rst_n) ...; it acts immediately. Async reset responds without a clock but needs reset-recovery/removal timing care; sync reset is simpler for timing but needs a running clock.

When two statements scheduled in the same time step have no defined order, so the result depends on simulator implementation — classically, reading and writing the same reg with blocking assignments across two always blocks at the same edge. Non-blocking assignments for sequential logic and clocking disciplines eliminate most races.

It schedules a statement in the Inactive region of the current time step — after other active events but at the same time. It is sometimes used to dodge a race, but it creates fragile, order-dependent behaviour and is considered a code smell; fix the race with proper non-blocking/clocking instead.

Generally no — initial blocks are for testbenches and simulation. Some FPGA tools honour initial for register power-up values, but for ASICs you must use an explicit reset. Never rely on initial for design behaviour.