4:1 Multiplexer: Truth Table and Design

A 4 to 1 multiplexer is one of the most fundamental building blocks in digital logic design. It is a combinational circuit that routes one of four data inputs to a single output line, with the choice governed by two control signals called select lines. Because of its simplicity and versatility, the 4:1 multiplexer appears everywhere: in data routing, arithmetic circuits, communication systems, and even as a universal logic element that can implement any Boolean function. This reference article explains what a multiplexer is, derives the 4:1 MUX truth table and Boolean expression, walks through its gate-level implementation, and shows how to scale it up to a 16:1 MUX, use it as a full adder, and describe it in Verilog.

What Is a Multiplexer?

A multiplexer (often abbreviated MUX) is a data selector. Imagine several incoming data lines and a single outgoing line: a multiplexer acts like a rotary switch that connects exactly one input to the output at any instant. The switch position is set electronically by a group of select (or control) lines rather than by hand.

The relationship between inputs and select lines is fixed: a multiplexer with n select lines can choose among 2ⁿ data inputs. So a 2:1 MUX needs 1 select line, a 4:1 MUX needs 2, an 8:1 MUX needs 3, and a 16:1 MUX needs 4. Multiplexers are classic examples of combinational circuits, because the output depends only on the present inputs and never on any stored past state.

The reverse operation is performed by a demultiplexer, which takes a single input and routes it to one of many outputs. Together, the MUX and DEMUX pair is the foundation of time-division multiplexing in digital communication.

4:1 Multiplexer: Block Diagram and Terminals

A 4×1 multiplexer (also written 4:1 MUX or “mux 4 to 1”) has the following terminals:

• Four data inputs: I₀, I₁, I₂, I₃
• Two select lines: S₁ (most significant) and S₀ (least significant)
• One output: Y

Conceptually, the block diagram of the mux is a trapezoidal or rectangular block with the four inputs entering on the left, the two select lines entering from the bottom, and the single output Y leaving on the right. The two select lines form a 2-bit binary number whose decimal value (0, 1, 2, or 3) identifies which data input is forwarded to Y. For example, when S₁S₀ = 10 (decimal 2), the multiplexer connects input I₂ to the output.

4 to 1 Multiplexer Truth Table

Because the data inputs can each be 0 or 1, a full truth table would have 64 rows. Instead, engineers use a compact function table that lists the output in terms of the selected input. This is the standard way the 4 to 1 multiplexer truth table is written:

The table reads directly: the binary select code points to the input index that reaches the output. This one-to-one mapping between the select value and the input subscript is what makes multiplexers so easy to reason about.

Boolean Output Expression

From the function table, each row contributes a product term in which the selected input is ANDed with the corresponding minterm of the select lines. Summing the four terms gives the Boolean output expression of the 4:1 multiplexer:

Y = S₁′S₀′I₀ + S₁′S₀I₁ + S₁S₀′I₂ + S₁S₀I₃

Here the prime symbol (′) denotes logical NOT. Notice that exactly one of the four AND terms can be active for any given select combination, because the four select minterms are mutually exclusive. That guarantees a single, unambiguous input is passed to Y. This equation also maps neatly onto a Karnaugh map, which is a useful exercise for verifying that the select minterms cover all cases without overlap.

Gate-Level Implementation

Translating the Boolean expression into hardware requires the following gates:

• Two NOT gates to produce the complements S₁′ and S₀′.
• Four 3-input AND gates, one per data input. Each AND gate receives one data input and the appropriate true/complement combination of the select lines.
• One 4-input OR gate that combines the four AND outputs into Y.

The wiring follows the expression term by term:

1. AND gate 1: I₀ · S₁′ · S₀′
2. AND gate 2: I₁ · S₁′ · S₀
3. AND gate 3: I₂ · S₁ · S₀′
4. AND gate 4: I₃ · S₁ · S₀

The four products feed the OR gate, whose output is the multiplexer output Y. In practice, designers frequently build the same function entirely from NAND gates, since NAND is a universal gate and maps efficiently onto CMOS technology. The two-level AND-OR topology is what makes the multiplexer fast: a signal passes through at most one inverter, one AND gate, and one OR gate.

Building a 16:1 Multiplexer from 4:1 MUXes

Larger multiplexers can be constructed hierarchically from smaller ones, a technique known as tree or cascade expansion. To build a 16:1 multiplexer from 4:1 MUXes, you need five 4:1 multiplexers arranged in two stages, controlled by four select lines S₃S₂S₁S₀:

• First stage – four 4:1 MUXes: Partition the 16 inputs into four groups of four. Each first-stage MUX uses the lower two select lines S₁ and S₀. The first MUX handles inputs 0–3, the second handles 4–7, the third 8–11, and the fourth 12–15.
• Second stage – one 4:1 MUX: The four first-stage outputs become the data inputs of a single final MUX, which is driven by the upper two select lines S₃ and S₂.

The upper bits choose which group is active, and the lower bits choose the line within that group, so the full 4-bit select code uniquely addresses one of the 16 inputs. The same divide-and-address principle scales further: an 8:1 MUX needs one extra select line and two 4:1 MUXes feeding a 2:1 stage, and the pattern repeats for any power-of-two width.

Implementing a Full Adder Using a 4:1 MUX

A powerful property of multiplexers is that a MUX with n select lines can realize any Boolean function of n+1 variables. For a function of three variables, we use the two select lines for two variables and feed the third variable (or its complement, or a constant 0/1) into the data inputs. A full adder adds three bits — A, B, and carry-in C_in — and produces Sum and C_out.

Choose A and B as the select lines (S₁ = A, S₀ = B) and treat C_in as the data variable. Working through the full-adder truth table for each select combination gives:

So the Sum output is produced by a 4:1 MUX with data inputs I₀ = C_in, I₁ = C_in′, I₂ = C_in′, I₃ = C_in. The Carry-out output is produced by a second 4:1 MUX with data inputs I₀ = 0, I₁ = C_in, I₂ = C_in, I₃ = 1. A single inverter supplies C_in′, and two multiplexers deliver a complete full adder.

Implementing a General Boolean Function

The same method implements any three-variable function F(A, B, C). Pick A and B as select lines, then for each of the four select combinations inspect the two truth-table rows (C = 0 and C = 1) and set the corresponding data input to 0, 1, C, or C′. This “MUX-as-lookup-table” approach is the conceptual ancestor of the LUTs inside modern FPGAs, and it reinforces why multiplexers are considered universal logic primitives.

Verilog Example

In register-transfer-level design, a 4:1 multiplexer is typically described behaviorally rather than gate by gate. A concise, synthesizable description uses a case statement inside a combinational always block:

module mux4to1 (
    input  wire [3:0] I,      // data inputs I0..I3
    input  wire [1:0] S,      // select lines S1,S0
    output reg        Y       // output
);
    always @(*) begin
        case (S)
            2'b00 : Y = I[0];
            2'b01 : Y = I[1];
            2'b10 : Y = I[2];
            2'b11 : Y = I[3];
            default : Y = 1'b0;
        endcase
    end
endmodule

The same block can also be written as a single continuous assignment, assign Y = I[S];, which lets the synthesis tool infer the multiplexer directly. Behavioral modeling keeps the intent clear and portable; for a deeper look at language choices, see our comparison of Verilog and SystemVerilog. Mastering constructs like these is a core part of professional digital design.

If you want to build real, interview-ready skills in RTL coding, combinational and sequential design, and FPGA/ASIC flows, explore our Advanced RTL Design Course (online and offline) at ChipXpert.

Frequently Asked Questions

What is a 4 to 1 multiplexer?

A 4 to 1 multiplexer is a combinational circuit with four data inputs, two select lines, and one output. The two select lines form a binary code that chooses which of the four inputs is connected to the output, following the rule that the select value equals the index of the selected input.

How many select lines does a 4×1 multiplexer need?

A 4×1 multiplexer needs two select lines. In general a multiplexer with n select lines can route 2ⁿ inputs, and since 2² = 4, two select lines (S₁ and S₀) are exactly enough to address four inputs.

What is the Boolean expression for a 4:1 MUX?

The output expression is Y = S₁′S₀′I₀ + S₁′S₀I₁ + S₁S₀′I₂ + S₁S₀I₃. Each product term ANDs one data input with the unique select-line minterm that activates it, and the four terms are summed with an OR gate.

How many 4:1 multiplexers are required to build a 16:1 multiplexer?

You need five 4:1 multiplexers: four in the first stage to handle the sixteen inputs in groups of four (using the two lower select bits) and one in the second stage to select among those four results (using the two upper select bits).

Can a multiplexer implement any logic function?

Yes. A multiplexer acts as a lookup table, so a MUX with n select lines can implement any Boolean function of n+1 variables by driving its data inputs with the appropriate constants or single-variable terms. This is why multiplexers are used to realize functions such as full adders and why their principle underlies FPGA logic cells.

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