One’s and Two’s Complement in Binary

Every digital system that performs arithmetic needs a way to represent negative numbers using nothing but 0s and 1s. The most widely used scheme in modern processors, from an 8-bit microcontroller to a 64-bit CPU, is two’s complement. To understand why it dominates, it helps to walk through its simpler predecessors first: the sign-magnitude idea and one’s complement. This reference article explains how to compute each binary complement, how signed numbers and their ranges work, how two’s complement turns subtraction into addition, and how hardware detects overflow.

What Is a Binary Complement?

A binary complement is a transformed version of a binary number used to encode its negative. Two complement systems matter in digital logic:

• One’s complement (1s complement): invert every bit — change each 0 to 1 and each 1 to 0. This is a pure bitwise NOT operation.
• Two’s complement (2’s complement): take the one’s complement and then add 1 to the least significant bit (LSB).

Both schemes reserve the most significant bit (MSB) as a sign bit: 0 marks a non-negative number and 1 marks a negative number. The difference lies entirely in how the remaining magnitude is encoded.

One’s Complement: Bit Inversion

To form the one’s complement of a number, you invert all its bits. Because inversion is exactly what a NOT gate does, one’s complement is trivial to build in hardware — a bank of inverters, one per bit. If you want to review the gates behind this, see our guide to universal gates, which covers how NOT behaviour is derived from NAND and NOR.

Consider the 8-bit value +5 = 00000101. Inverting each bit gives its one’s complement, which represents -5 in the one’s complement system.

A defining quirk of one’s complement is that it has two representations of zero. Positive zero is 0000 0000 and negative zero is 1111 1111. This dual zero complicates comparison and arithmetic hardware, which is a major reason the system was eventually displaced.

Range of One’s Complement

For an n-bit word, one’s complement spans -(2^n-1 – 1) to +(2^n-1 – 1). The two zero patterns consume one otherwise usable code. For 8 bits that range is -127 to +127.

Two’s Complement: Invert and Add One

Two’s complement fixes the dual-zero problem and makes arithmetic uniform. The procedure to negate a number is:

1. Write the magnitude in binary using the full word width.
2. Invert every bit (form the one’s complement).
3. Add 1 to the LSB.

Returning to +5 = 00000101, the two’s complement that encodes -5 is computed as follows.

You can verify this: in an 8-bit field the pattern 1111 1011 equals 251 unsigned, and 256 – 251 = 5, so it correctly represents -5. A useful shortcut for forming two’s complement by hand: copy bits from the LSB upward until you reach the first 1 (copy that 1 too), then invert every bit above it. Applying that to 0000 0101 again yields 1111 1011 directly.

Interpreting a Two’s Complement Number

The value of an n-bit two’s complement number is found by giving the MSB a negative weight. For an 8-bit number the bit weights are -128, 64, 32, 16, 8, 4, 2, 1. The table below shows several encodings.

Range of Two’s Complement

For an n-bit word, two’s complement spans -2^n-1 to +2^n-1 – 1. For 8 bits that is -128 to +127. The range is asymmetric: there is one more negative value than positive, because only a single zero pattern (0000 0000) is needed, freeing the 1000 0000 code to represent the most negative number.

Comparing the Signed Representations

The three classic signed schemes handle the same bit patterns differently. The comparison below uses a 4-bit word for compactness.

One’s complement addition requires an end-around carry: any carry out of the MSB must be added back into the LSB to get the correct result. Two’s complement needs no such correction — the carry out is simply discarded — which is precisely why it won.

Binary Subtraction Using Two’s Complement

The headline benefit of two’s complement is that subtraction becomes addition. To compute A – B, the processor forms the two’s complement of B and adds it to A using the same adder it uses for ordinary addition. There is no dedicated subtractor circuit. If you want to see the ripple-carry hardware that performs the sum, our article on the full adder and half adder walks through the building blocks.

Worked Example: 7 – 5

Compute 7 – 5 in 8-bit two’s complement, which should yield +2.

1. 7 = 0000 0111
2. 5 = 0000 0101; its two’s complement (-5) = 1111 1011
3. Add: 0000 0111 + 1111 1011

The carry out of the MSB is thrown away, and the remaining 8 bits give 0000 0010 = +2, the correct answer.

Worked Example: 5 – 7

Now compute 5 – 7, expecting -2.

No carry leaves the MSB. The result 1111 1110 has sign bit 1, so it is negative; decoding it (invert and add 1 gives 0000 0010 = 2) confirms the value is -2.

Overflow Detection

Because a fixed-width word can only hold a limited range, adding two in-range numbers can produce a result that falls outside the range. This is signed overflow, and it must be detected because the stored result is wrong. The key rule:

• Overflow can only occur when the two operands have the same sign. Adding a positive and a negative number can never overflow.
• Overflow is flagged when the sign of the result differs from the common sign of the operands.
• Equivalently, in hardware: overflow = (carry into the MSB) XOR (carry out of the MSB).

Consider a 4-bit example adding +4 and +5 (both positive, expected +9, which exceeds the +7 maximum):

Two positive inputs produced a negative-looking result, so the overflow flag is set. Note that the carry-out of the MSB here is 0, yet overflow still occurred — proof that carry-out alone is not a reliable overflow indicator for signed arithmetic. The carry-out flag matters for unsigned arithmetic; the overflow flag matters for signed arithmetic, and processors maintain both separately.

Why Two’s Complement Dominates Hardware

Three properties make two’s complement the standard in arithmetic logic units (ALUs):

• Single zero simplifies equality and comparison logic.
• One adder does everything — addition and subtraction share the same datapath, saving silicon area and power.
• Sign extension is trivial: to widen a number, just replicate the sign bit. Extending 1011 (-5 in 4-bit) to 8 bits gives 1111 1011, still -5.

These behaviours are exactly what you model when writing RTL for datapaths, and they interact closely with the combinational and sequential logic around them. If you are learning how arithmetic blocks sit inside larger designs, our overview of sequential circuits and related binary encodings such as binary to Gray code conversion provide helpful context for how numbers flow through registers and counters.

Take Your Digital Design Skills Further

Mastering number systems is the foundation for building real arithmetic hardware in Verilog and SystemVerilog. If you are ready to design adders, ALUs, and signed datapaths that actually synthesize, explore the Advanced RTL Design course at ChipXpert to put these concepts into production-quality RTL.

Frequently Asked Questions

What is the main difference between one’s complement and two’s complement?

One’s complement negates a number by inverting all its bits, while two’s complement inverts all the bits and then adds 1 to the LSB. The extra “+1” step gives two’s complement a single representation of zero and lets subtraction run on a plain adder, which is why it is preferred in modern processors.

How do you find the two’s complement of a binary number quickly?

Use the copy-and-invert shortcut: scan from the LSB upward, copy each bit (including the first 1 you encounter) unchanged, then invert every bit to the left of that first 1. This produces the two’s complement in a single pass without a separate add step.

What is the range of an 8-bit two’s complement number?

An 8-bit two’s complement word represents values from -128 to +127. The range is asymmetric because only one bit pattern is needed for zero, leaving one extra code (1000 0000) available for the most negative value.

Why is overflow not the same as carry-out in two’s complement?

Carry-out indicates that an unsigned result exceeded the word width. Signed overflow, however, depends on the sign bits: it occurs when two operands of the same sign produce a result with the opposite sign. A computation can set the carry flag without overflowing, or overflow without a carry-out, so the two flags are tracked independently.

Does two’s complement require special hardware for subtraction?

No. That is its central advantage. To compute A – B, the hardware forms the two’s complement of B and feeds it into the same adder used for addition, discarding any final carry-out. No dedicated subtractor circuit is needed.