SR Latch Using NAND and NOR Gates

The SR latch (Set-Reset latch) is the most fundamental sequential storage element in digital electronics. Unlike a combinational circuit, whose output depends only on present inputs, a latch can remember a single bit of information: it has memory. Every flip-flop, register, and on-chip SRAM cell can be traced back conceptually to this two-gate feedback loop. In this reference we build the SR latch from the ground up using both NOR gates and NAND gates, derive the correct truth table for each, examine why one input combination is called forbidden, and then extend the circuit into a gated (clocked) SR latch. We close by drawing the precise distinction between a latch and a flip-flop.

What Is an SR Latch?

An SR latch is a bistable circuit built from two cross-coupled logic gates. “Bistable” means it has two stable states that it can hold indefinitely as long as power is applied: a stored logic 1 and a stored logic 0. The circuit exposes two outputs, conventionally labelled Q and Q′ (Q-bar, the complement). Under normal operation Q and Q′ are always opposite, which is why the latch is said to store a single bit.

The two control inputs are S (Set) and R (Reset):

• Set drives the stored bit to Q = 1.
• Reset drives the stored bit to Q = 0.
• When neither Set nor Reset is asserted, the latch holds its previous value — this is the memory behaviour.

The “latch sr” structure works because the output of each gate is fed back into the input of the other. This positive feedback is what gives the circuit its ability to latch, or lock onto, a state. Because feedback is involved, the SR latch belongs firmly to the family of sequential circuits rather than to purely combinational logic.

SR Latch Using NOR Gates (Active-High)

The classic SR latch is built from two cross-coupled NOR gates. One NOR gate produces Q; the other produces Q′. The S input feeds the gate that generates Q′, and the R input feeds the gate that generates Q, with each gate’s output routed back to the second input of the other gate.

Recall the behaviour of a NOR gate: its output is 1 only when all inputs are 0; if any input is 1, the output is forced to 0. This single rule is enough to derive the entire operation of the NOR SR latch. Because a logic 1 on an input is what triggers an action, the NOR latch is said to have active-high inputs.

Deriving the NOR Latch Behaviour

• S = 0, R = 0 (Hold): With both inputs 0, each NOR gate’s output is decided purely by the feedback from the other gate. The loop reinforces whatever was already stored, so Q keeps its previous value Q(prev).
• S = 1, R = 0 (Set): A 1 on S forces the Q′ gate output to 0. That 0 feeds back into the Q gate, which (with R = 0) now sees 0 and 0, driving Q to 1. The latch is set.
• S = 0, R = 1 (Reset): A 1 on R forces Q to 0. That 0 feeds back into the Q′ gate, which (with S = 0) drives Q′ to 1. The latch is reset.
• S = 1, R = 1 (Forbidden): Both NOR gates are forced to output 0, so Q = 0 and Q′ = 0 simultaneously. This violates the rule that Q and Q′ must be complementary.

NOR SR Latch Truth Table

The characteristic (next-state) Boolean expression for the NOR SR latch is:

Q(next) = S + R′ · Q(prev), valid under the constraint S · R = 0 (the two inputs must never both be 1).

SR Latch Using NAND Gates (Active-Low)

The “sr latch using nand gates” is the second canonical form, and it is extremely common in textbooks and in real silicon because NAND is a natural, compact gate in CMOS. Here two NAND gates are cross-coupled in the same topology. However, the NAND version behaves in a mirror-image way: its inputs are active-low, meaning a logic 0 triggers the action. To emphasise this, the inputs are usually drawn as S̄ and R̄ (S-bar and R-bar).

Recall the NAND gate rule: its output is 0 only when all inputs are 1; if any input is 0, the output is forced to 1. The NAND and NOR gates are both universal gates, so either can implement the full latch, but their active levels are opposite.

Deriving the NAND Latch Behaviour

• S̄ = 1, R̄ = 1 (Hold): With both inputs inactive (high), each gate output depends only on the feedback, so the latch holds its previous state.
• S̄ = 0, R̄ = 1 (Set): A 0 on S̄ forces the Q gate output to 1, so Q = 1. The latch is set.
• S̄ = 1, R̄ = 0 (Reset): A 0 on R̄ forces the Q′ gate output to 1, pulling Q to 0. The latch is reset.
• S̄ = 0, R̄ = 0 (Forbidden): Both NAND gates are forced to output 1, so Q = 1 and Q′ = 1 at the same time, again breaking complementarity.

NAND SR Latch (Active-Low) Truth Table

Notice the symmetry: the NAND latch “sr latch nand gate” implementation is identical in structure to the NOR version but has its Set, Reset, Hold, and Forbidden rows mapped to the opposite input polarity. A simple way to remember it: in the NAND latch the inactive (idle) input level is 1 1, whereas in the NOR latch the inactive level is 0 0.

The Forbidden / Invalid State

Every “s r latch” shares one dangerous input combination. In the NOR latch it is S = R = 1; in the NAND latch it is S̄ = R̄ = 0. Two problems arise in this condition:

1. Loss of complementarity. Both outputs take the same value (00 for NOR, 11 for NAND). The whole point of the latch is that Q and Q′ are opposites, so any downstream logic that assumes Q′ = NOT Q will misbehave.
2. The race condition. The real hazard appears when the forbidden inputs are released simultaneously, returning the latch to the hold condition. Because the two gates have slightly different propagation delays, the circuit cannot predict which gate will win the feedback race. The latch may settle to Q = 1 or Q = 0 essentially at random, and in pathological cases it can oscillate or enter a metastable state.

For this reason the condition is labelled forbidden, invalid, or indeterminate, and well-designed systems guarantee that both inputs are never asserted together. Eliminating this hazard is one of the motivations behind the D latch and the D flip-flop, which make it structurally impossible to assert Set and Reset at once.

Gated (Clocked) SR Latch

A plain SR latch responds to its inputs continuously; the instant S or R changes, Q may change. In a larger system we usually want the latch to accept new data only at controlled moments. The gated SR latch (also called a clocked or enabled SR latch) adds an Enable input, often labelled E or CLK.

The gated latch is built by placing two AND (or NAND) gates in front of the basic cross-coupled latch. Each steering gate takes one data input (S or R) and the common Enable line. When Enable = 0, both steering-gate outputs are held at the latch’s inactive level, so S and R are blocked and the latch simply holds its stored bit regardless of how S and R wiggle. When Enable = 1, S and R pass through and the latch behaves exactly like the basic SR latch described above.

Gated SR Latch Truth Table

Here X denotes a don’t-care input. The gated SR latch is level-sensitive: it is “transparent” during the entire interval that Enable is high, meaning the output tracks the inputs throughout that window. This transparency is the defining feature of a latch and the key point that separates it from a flip-flop. Grouping these input conditions and minimising the steering logic is a natural application of a Karnaugh map.

Timing, Setup, and Hold

Because the gated SR latch is level-sensitive, data must be stable while Enable is asserted. Two timing parameters govern reliable operation:

• Setup time: the minimum time the S/R inputs must be steady before the enabling edge or window.
• Hold time: the minimum time the inputs must remain steady after the latch captures data.

Violating setup or hold time can push the latch into metastability, a condition where Q hovers near an invalid intermediate voltage before eventually resolving unpredictably. In synchronous design this risk is one reason engineers prefer edge-triggered flip-flops, which sample data only at a single instant and therefore have a much narrower vulnerability window.

Latch vs Flip-Flop

Students often use “latch” and “flip-flop” interchangeably, but in digital design they are distinct:

A flip-flop is typically built by chaining two latches in a master-slave configuration so that data is captured on one clock edge rather than throughout a level. The widely used JK flip-flop goes a step further by redefining the forbidden SR input combination (both inputs high) as a useful toggle operation, removing the invalid state altogether. Flip-flops in turn become the state-holding elements of a finite state machine.

Why the SR Latch Matters

The SR latch is small, but mastering it unlocks the rest of sequential logic. The cross-coupled feedback concept reappears in the D latch, the D and JK flip-flops, counters, shift registers, and the six-transistor SRAM bit cell. Understanding the Set, Reset, Hold, and Forbidden behaviours — and why NAND and NOR implementations invert the active level — builds the intuition you need to reason about timing, metastability, and state retention in real hardware. When you move on to describing these elements in a hardware description language, the same truth tables map directly onto RTL constructs, which is where careful coding style keeps simulation and synthesis in agreement.

Ready to go from gate-level latches to synthesizable RTL? ChipXpert’s Advanced RTL Design Course (online and offline) walks you through sequential element design, clocking, timing, and FSMs with hands-on labs — the natural next step after mastering the SR latch.

Frequently Asked Questions

What is the difference between an SR latch using NAND gates and one using NOR gates?

Both are cross-coupled, two-gate bistable circuits that store one bit, but they differ in active level. The NOR-gate SR latch has active-high inputs: S = 1 sets and R = 1 resets, with 0 0 being the hold state and 1 1 being forbidden. The NAND-gate SR latch (an sr latch using nand gates) has active-low inputs S̄ and R̄: a 0 sets or resets, 1 1 is the hold state, and 0 0 is forbidden. Functionally they are mirror images of each other.

Why is the S = R = 1 state called forbidden in an SR latch?

When both Set and Reset are asserted in a NOR-gate latch, both outputs are forced to the same level (0 0), so Q and Q′ are no longer complementary. Worse, when the inputs are released at the same time, gate propagation-delay differences create a race condition and the latch settles to an unpredictable state. Because the result cannot be guaranteed, the combination is labelled forbidden or invalid. For a NAND-gate latch the equivalent forbidden input is S̄ = R̄ = 0.

What is a gated SR latch?

A gated (or clocked) SR latch adds an Enable input to the basic SR latch through a pair of steering gates. When Enable is low, the S and R inputs are blocked and the latch holds its stored value; when Enable is high, the latch becomes transparent and responds to S and R normally. It is level-sensitive, meaning the output can change at any time while Enable remains high.

Is an SR latch the same as an SR flip-flop?

No. A latch is level-sensitive and is transparent for the entire time its enable is active, whereas a flip-flop is edge-triggered and captures data only at a single clock transition. An SR flip-flop is usually constructed from latches in a master-slave arrangement so that it responds to a clock edge rather than a clock level, giving more predictable timing for synchronous systems.

What does the characteristic equation Q = S + R′·Q represent?

It is the next-state (characteristic) equation of the NOR SR latch. It states that the next output is 1 whenever Set is asserted, or when Reset is not asserted and the previous stored value was already 1 (the hold condition). The equation is valid only under the constraint S·R = 0, which simply formalises the rule that Set and Reset must never be asserted together.