T Flip-Flop: Truth Table, Circuit and Working

The T flip-flop, or toggle flip-flop, is one of the most elegant storage elements in digital logic. It has a single data input, T, and a clock. On every active clock edge it does exactly one of two things: hold its current state, or invert it. That simple behaviour makes it the natural building block for frequency dividers and binary counters. In this reference we work through the T flip flop truth table, its characteristic and excitation tables, the Boolean equation that governs it, how it is derived from JK and D flip-flops, its role in ripple counters, and a clean behavioural Verilog model.

What Is a T Flip-Flop?

A T flip-flop is an edge-triggered sequential element with one control input T (toggle) and an output Q (with its complement Q̅). Being a sequential circuit, its next output depends not only on the present input but also on the currently stored state. The rule is deliberately minimal:

• When T = 0, the flip-flop retains its stored value — Q does not change at the clock edge.
• When T = 1, the flip-flop toggles — Q becomes the complement of its previous value.

Because it changes state only at a defined clock transition (typically the rising edge), the T flip-flop is synchronous. Between clock edges the output is stable regardless of what T is doing, which is what makes these elements safe to cascade.

T Flip-Flop Truth Table

The truth table of T flip flop captures the toggle behaviour as a function of the current state Q(t) and the input T. Here Q(t) is the present output and Q(t+1) is the output after the next active clock edge.

Reading the table, the two rows where T = 0 leave Q unchanged, while the two rows where T = 1 flip Q to its opposite value. This is the defining signature of the device.

Characteristic Table and Characteristic Equation

The characteristic table is simply a compact restatement of the truth table, listing the next state purely in terms of T and Q(t).

If you examine when Q(t+1) equals 1, it happens when T = 0 and Q = 1, or when T = 1 and Q = 0. That is precisely the exclusive-OR of T and Q. The characteristic equation of the T flip-flop is therefore:

Q(t+1) = T ⊕ Q(t) = T·Q̅(t) + T̅·Q(t)

This single XOR expression is worth memorising — it tells you everything the device does. If you are rusty on how XOR simplifies or on grouping terms, a quick refresher with a Karnaugh map makes the derivation obvious, and XOR itself can be built entirely from universal gates such as NAND or NOR.

Excitation Table

The excitation table answers the inverse question that designers actually need when building counters and state machines: given a desired transition from Q(t) to Q(t+1), what value must T take? For a T flip-flop this is beautifully simple — T must be 1 whenever the output needs to change, and 0 whenever it must stay put.

In other words, T = Q(t) ⊕ Q(t+1). This compact excitation rule is a major reason T flip-flops dominate counter design: the drive logic for each stage reduces to detecting whether that bit must flip.

Logic Diagram of T Flip-Flop

There is no “native” transistor-level T flip-flop in most standard-cell libraries; instead the toggle function is realised by wiring a more general flip-flop so that it implements Q(t+1) = T ⊕ Q(t). The two classic constructions are from a JK flip-flop and from a D flip-flop.

T Flip-Flop from a JK Flip-Flop

A JK flip-flop toggles when both J and K are 1 and holds when both are 0. The logic diagram of t flip flop built from JK is the simplest derivation of all: just tie the J and K inputs together and call that common line T.

• T = 0 → J = 0, K = 0 → JK holds its state.
• T = 1 → J = 1, K = 1 → JK toggles.

The JK characteristic equation Q(t+1) = J·Q̅ + K̅·Q collapses, under J = K = T, to Q(t+1) = T·Q̅ + T̅·Q = T ⊕ Q — exactly the T flip-flop equation. If the JK flip-flop and its own race-around considerations are unfamiliar, the dedicated JK flip-flop reference covers them in depth.

T Flip-Flop from a D Flip-Flop

A D flip-flop obeys Q(t+1) = D. To make it toggle, we must feed it the value we want next, which the characteristic equation already gives us: Q(t+1) = T ⊕ Q(t). So the construction is:

1. Take a D flip-flop with output Q and complement Q̅.
2. Place a two-input XOR gate in front of D.
3. Drive the XOR with T and the fed-back output Q.
4. Connect the XOR output to the D input, so D = T ⊕ Q.

On each clock edge the D flip-flop loads D = T ⊕ Q, which is the desired next state. When T = 0 the XOR passes Q unchanged (hold); when T = 1 the XOR inverts Q (toggle). This XOR-plus-D structure is the form most often seen inside synthesised RTL, because synthesis tools target D flip-flops and simply add combinational logic in front of them.

Timing and Edge Triggering

Like all practical flip-flops, the T flip-flop samples its input at a clock edge rather than during a level. Edge triggering avoids the “race-around” problem that afflicts level-sensitive toggle latches, where a T = 1 input held during a wide active clock could cause the output to oscillate several times within one clock pulse. With a positive-edge-triggered design, exactly one toggle occurs per rising edge no matter how long T stays high. Real devices also carry setup and hold-time requirements on T relative to the clock edge; violating them risks metastability, so T must be stable through the sampling window.

T Flip-Flop in Ripple Counters

The most important application of the T flip-flop is the asynchronous (ripple) counter. Configure a flip-flop with T permanently tied to 1 and it toggles on every clock edge, so its output is a clean divide-by-two of the clock frequency. Chain several such stages, each clocked by the previous stage’s output, and you get a binary ripple counter:

• The first stage toggles every input clock edge → it produces the least-significant bit.
• Each subsequent stage toggles half as often as the one before it, producing the next binary weight.
• With n stages you count through 2ⁿ states, from 0 up to 2ⁿ−1, then roll over.

Because each stage is clocked by the preceding output, the transitions “ripple” through the chain, which introduces cumulative propagation delay — the reason ripple counters are simple but comparatively slow. Synchronous counters instead clock every stage from the same clock and compute each stage’s T input from the lower bits (stage k toggles only when all lower bits are 1), trading extra combinational logic for uniform timing. Both styles are standard components inside any finite state machine or datapath that needs counting or frequency division.

T Flip-Flop Verilog Code

A behavioural model is the clearest way to express the toggle rule in RTL. The following positive-edge-triggered T flip-flop includes an active-low asynchronous reset, which is the common convention in synchronous design.

module t_flip_flop (
    input  wire clk,       // clock
    input  wire rst_n,     // active-low asynchronous reset
    input  wire t,         // toggle input
    output reg  q          // stored state
);

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n)
            q <= 1'b0;     // clear on reset
        else if (t)
            q <= ~q;       // toggle
        else
            q <= q;        // hold
    end

endmodule

The line q <= ~q; directly implements Q(t+1) = T ⊕ Q under T = 1, while the else branch holds the state under T = 0. Note the non-blocking assignment (<=) inside the clocked block — this is essential for correct sequential behaviour and matches the way hardware registers update simultaneously on the edge. A behavioural style like this is preferred over structurally instantiating a D flip-flop and an XOR gate, because it lets the synthesis tool map the intent to whatever flip-flop cell the target library provides. If you are weighing language features for larger designs, the comparison of Verilog vs SystemVerilog is a useful companion read.

Synchronous-Reset Variant

For many FPGA and ASIC flows a synchronous reset is preferred. The only change is to move the reset check inside the clock-edge sensitivity:

always @(posedge clk) begin
    if (!rst_n) q <= 1'b0;
    else if (t) q <= ~q;
end

Choosing between asynchronous and synchronous reset is a project-level decision driven by your library and timing constraints, but the toggle logic itself is identical.

T Flip-Flop vs D and JK Flip-Flops

Seeing the three common flip-flops side by side clarifies when to reach for each.

The D flip-flop is the universal storage element and the synthesis target of choice. The JK flip-flop is the most flexible, offering hold, set, reset, and toggle. The T flip-flop is the specialist: a one-input device whose toggle-or-hold behaviour makes counter and divider design remarkably compact.

Common Mistakes to Avoid

• Confusing level and edge behaviour. A T flip-flop toggles once per clock edge, not continuously while T is high.
• Forgetting the feedback in the D-based construction. The XOR must take the fed-back Q, not a constant — D = T ⊕ Q, not D = T.
• Using blocking assignments in the clocked block. Always use non-blocking (<=) for sequential logic to model register updates correctly.
• Ignoring ripple delay. In asynchronous counters, cumulative stage delay limits maximum count frequency.

Master Flip-Flops and RTL Design

Flip-flops are the heartbeat of every synchronous system, and fluency with the T flip-flop — its truth table, characteristic equation, and counter applications — is a core skill for anyone entering VLSI. If you want structured, project-based training that takes you from these fundamentals through complete RTL design and verification, explore the ChipXpert Advanced RTL Design Course (online & offline) and build these circuits hands-on.

Frequently Asked Questions

What is the truth table of a T flip flop?

The t flip flop truth table has four rows based on the input T and the present state Q. When T = 0 the output holds (0→0 and 1→1); when T = 1 the output toggles (0→1 and 1→0). It is summarised by the equation Q(t+1) = T ⊕ Q(t).

What is the characteristic equation of a T flip flop?

The characteristic equation is Q(t+1) = T ⊕ Q(t), which expands to Q(t+1) = T·Q̅(t) + T̅·Q(t). It states that the next output is the exclusive-OR of the toggle input and the current stored value.

How do you build a T flip flop from a D flip flop?

Place a two-input XOR gate ahead of the D input and drive it with T and the fed-back output Q, so D = T ⊕ Q. On each clock edge the D flip-flop loads this value, holding when T = 0 and toggling when T = 1. You can equally build one from a JK flip-flop by tying J and K together to form T.

Why is the T flip flop used in counters?

With T tied to 1 a T flip-flop toggles every clock edge, producing a divide-by-two output. Cascading these stages creates a binary ripple counter, and because the excitation rule is simply T = Q(t) ⊕ Q(t+1), the drive logic for each stage is minimal — making T flip-flops ideal for counting and frequency division.

How is a T flip flop written in Verilog?

A behavioural t flip flop verilog model uses a clocked always block: on posedge clk, if T is high assign q <= ~q; to toggle, otherwise hold. Non-blocking assignments and an optional reset (synchronous or asynchronous) complete the register so it synthesises to a standard flip-flop cell.

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