JK Flip-Flop Truth Table, Working and Types

The JK flip-flop is one of the most versatile sequential building blocks in digital electronics. It removes the single forbidden state that plagues the simple SR latch and, in its edge-triggered master-slave form, it can set, reset, hold, or toggle on every clock edge. Because of this flexibility it appears everywhere — counters, frequency dividers, shift registers, and state machines. This pillar article explains the JK flip-flop truth table, its characteristic and excitation tables, how it is built from NAND gates, the race-around problem and its master-slave fix, and then places it in the wider family of latches and flip-flops (SR latch, D, and T) before closing with the standard inter-conversions.

What Is a Flip-Flop?

A flip-flop is a one-bit memory element that stores a logic value (0 or 1) and changes state only in response to a control signal. Unlike a purely combinational circuit, whose output depends only on current inputs, a sequential element remembers past inputs. Two broad categories exist:

• Latches are level-sensitive — the output can follow the inputs for the entire duration that the enable or clock level is active.
• Flip-flops are edge-triggered — the output can change only at the instant of a rising or falling clock edge.

The JK flip-flop belongs to the second group. To understand why it was invented, we first look at the SR latch it improves upon.

The SR Latch

The SR latch (Set-Reset) is the simplest bistable element, built from two cross-coupled gates. With a NOR-based (active-high) SR latch, the behaviour is:

The condition S = R = 1 is forbidden because it forces both outputs to the same level, violating the complementary relationship between Q and Q′, and the final state becomes unpredictable when the inputs return to 0 simultaneously.

SR Latch Using NAND Gates

The SR latch using NAND gates is the classic cross-coupled version. Because NAND gates are active-low, the inputs are usually drawn as S′ and R′ (sometimes labelled S-bar and R-bar). Its behaviour is the complement of the NOR version:

Adding an enable input and a pair of steering NAND gates converts this S R latch into a gated SR latch, and gating it with a clock edge leads naturally toward the flip-flop family. The remaining weakness — a forbidden input combination — is exactly what the JK flip-flop eliminates.

The JK Flip-Flop

The JK flip-flop takes the clocked SR structure and feeds the outputs Q and Q′ back into the input gates. This feedback makes the previously forbidden combination (both inputs HIGH) useful: instead of being invalid, it toggles the stored bit. The inputs are named J (functionally like Set) and K (functionally like Reset).

JK Flip-Flop Truth Table

For a positive-edge-triggered JK flip-flop, with Q representing the present state and Q(next) the state after the active clock edge:

The defining advantage is the last row: J = K = 1 toggles the output, so every clock edge inverts the stored value. This is what makes the JK flip-flop ideal for binary counters.

Characteristic Table and Equation

The characteristic table expands the truth table to show the explicit next state for every combination of inputs and present state Q:

Minimising this gives the characteristic equation of the JK flip-flop:

Q(next) = J·Q′ + K′·Q

Excitation Table

The excitation table answers the design question “what inputs are required to move from a given present state to a desired next state?” It is essential for sequential circuit synthesis. Here X denotes a don’t-care:

The abundance of don’t-care conditions is precisely why the JK flip-flop usually yields the simplest, lowest-gate-count state machines compared with D or T designs.

JK Flip-Flop Circuit from NAND Gates

A basic clocked JK flip-flop is constructed from a NAND-based SR latch preceded by two 3-input steering NAND gates:

• The first steering gate receives J, the clock, and Q′.
• The second steering gate receives K, the clock, and Q.
• Their outputs drive the S and R inputs of the cross-coupled NAND latch.

Because Q and Q′ are fed back, the gate that is “armed” depends on the current state. When J = K = 1, feedback guarantees that exactly one steering gate is enabled, so the latch always flips to its opposite state rather than entering the forbidden condition.

The Race-Around Condition

A problem appears with the simple level-triggered JK flip-flop. Suppose J = K = 1 and the clock is held HIGH. The output toggles; but the feedback then re-arms the opposite gate, so it toggles again — and keeps toggling for as long as the clock stays HIGH. If the clock pulse width is greater than the propagation delay of the flip-flop, the output oscillates unpredictably. This continuous, uncontrolled toggling during a single active clock level is called the race-around condition.

The output at the falling edge is then indeterminate because it depends on exactly how many propagation delays fit inside the pulse. Two classical remedies exist: make the clock pulse narrower than the propagation delay (impractical and unreliable), or redesign the flip-flop to be truly edge-triggered. The standard solution is the master-slave configuration.

Why Master-Slave Fixes the Race-Around

A master-slave JK flip-flop cascades two clocked JK (or SR) stages with complementary clocking:

• The master latch is enabled while the clock is HIGH and reads the J, K inputs, but its output is not yet passed on.
• The slave latch is enabled while the clock is LOW (it receives the inverted clock), copying the master’s captured value to the final output.

Because the master and slave are never transparent at the same time, there is no feedback path that is active simultaneously with input sampling. The output can change at most once per clock pulse, eliminating the race-around condition and giving clean, predictable edge-triggered behaviour.

The D Flip-Flop

The D (Data or Delay) flip-flop has a single data input and simply stores whatever value is present at D on the active clock edge. It is derived from an SR or JK flip-flop by tying the two inputs together through an inverter (K = J′), removing all invalid and hold ambiguity.

Its characteristic equation is the simplest of all: Q(next) = D. The D flip-flop is the workhorse of registers, pipelines, and almost all synthesised RTL, which is why it dominates Verilog and SystemVerilog designs.

The T Flip-Flop

The T (Toggle) flip-flop is obtained by tying J and K together (T = J = K). When T = 0 it holds; when T = 1 it toggles. It is the natural element for ripple and synchronous counters. The T flip flop truth table is:

Its characteristic equation is Q(next) = T ⊕ Q (the XOR of the toggle input and the present state).

Latch vs Flip-Flop

Although the terms are often used loosely, latches and flip-flops differ in important ways that affect timing, power, and testability in real chips:

Conversion Between Flip-Flops

Any flip-flop can be converted into any other using its excitation table and a Karnaugh map. The general procedure is:

1. Write the characteristic table of the required flip-flop (the one you want to emulate).
2. For each present-to-next-state transition, read the available flip-flop’s excitation requirements.
3. Build K-maps for the available flip-flop’s inputs in terms of the required inputs and Q, then minimise.
4. Add the resulting combinational logic at the front of the available flip-flop.

Several standard results follow directly:

• JK → D: Set J = D and K = D′. The combined input then forces Q(next) = D.
• JK → T: Tie J = K = T. With both inputs equal, the device holds for T = 0 and toggles for T = 1.
• D → JK: Using the JK characteristic equation, the required logic is D = J·Q′ + K′·Q.
• T → D: Since a T flip-flop gives Q(next) = T ⊕ Q, feed D = T ⊕ Q into a D flip-flop.
• SR → JK: Steer the SR inputs with the JK outputs: S = J·Q′ and R = K·Q, which automatically avoids the forbidden S = R = 1 case.

Mastering these conversions is a core skill for RTL designers, because synthesis tools and standard-cell libraries may offer only a subset of flip-flop types, and because they reinforce the deeper point that all of these elements are different interfaces to the same one-bit memory.

Advance Your Digital Design Skills

If you want to move from understanding flip-flop truth tables to designing real sequential circuits, counters, and finite state machines in hardware description languages, explore the ChipXpert Advanced RTL Design course, where these concepts are applied hands-on in Verilog and SystemVerilog with industry-style projects. You may also find our guide on stick diagrams in VLSI layout useful once you progress from logic to physical implementation.

Frequently Asked Questions

What is the JK flip-flop truth table?

The JK flip-flop truth table has four input combinations. J = 0, K = 0 holds the current state; J = 0, K = 1 resets the output to 0; J = 1, K = 0 sets it to 1; and J = 1, K = 1 toggles the output to its complement. Its characteristic equation is Q(next) = J·Q′ + K′·Q.

What is the T flip flop truth table?

The T flip-flop has one input. When T = 0 the output holds its present value; when T = 1 the output toggles. In tabular form: T = 0 keeps Q unchanged (0→0, 1→1) and T = 1 inverts it (0→1, 1→0), giving the characteristic equation Q(next) = T ⊕ Q.

What is the difference between an SR latch and an S R latch using NAND gates?

A NOR-based SR latch is active-high: S = 1 sets and R = 1 resets, with S = R = 1 forbidden. An S R latch built from NAND gates is active-low, so its inputs are S′ and R′; the hold condition becomes both inputs HIGH, and the forbidden condition becomes both inputs LOW. The logic is identical in function but inverted in input polarity.

Why is the JK flip-flop better than the SR latch?

The SR latch has a forbidden input combination (both inputs asserted) that leaves the output undefined. The JK flip-flop feeds its outputs back into the input gates so that this combination performs a useful toggle instead. This removes the invalid state entirely and makes the device suitable for counters and dividers.

How does the master-slave configuration solve the race-around condition?

The race-around condition occurs when a level-triggered JK flip-flop toggles repeatedly while the clock stays HIGH. A master-slave design uses two cascaded latches clocked on opposite levels, so input sampling (master) and output updating (slave) never happen at the same time. As a result the output changes at most once per clock pulse, producing clean edge-triggered behaviour.