Universal Gates: NAND and NOR Explained

In digital logic design, a handful of basic gates — AND, OR, NOT, XOR and XNOR — describe almost every combinational function we care about. Yet when a chip is actually fabricated, designers lean heavily on just two gates: NAND and NOR. These are called universal gates because either one, used by itself, can build any other logic function. This article explains what a universal gate is, proves why NAND and NOR earn the title, and walks through implementing NOT, AND, OR, XOR and XNOR using only NAND and then only NOR — with correct truth tables and exact gate counts. It closes with why this property matters so much in CMOS and ASIC standard-cell design.

What Is a Universal Gate?

A universal gate is a logic gate from which every other Boolean function can be constructed, using only copies of that same gate and no other gate type. Formally, a set of operations is functionally complete if it can express any truth table. The pair {AND, OR, NOT} is functionally complete, because any Boolean expression can be written in sum-of-products or product-of-sums form. The remarkable fact is that both NAND and NOR are individually functionally complete: a single gate type is enough.

This works because NAND and NOR each combine a basic operation (AND or OR) with inversion. Since inversion is the one thing AND and OR alone cannot produce, bundling it into the gate gives you everything at once. XOR, XNOR, AND, OR and even buffers all fall out of repeated application. By contrast, AND, OR, XOR and XNOR are not universal on their own — none of them can produce a NOT (a true inversion of a single input) without help.

The Two Universal Gates and Their Truth Tables

NAND is "AND followed by NOT"; NOR is "OR followed by NOT". Their two-input truth tables are the foundation for everything that follows.

Building Every Gate Using Only NAND

We now derive each common function from NAND gates alone. The key identity is A NAND A = (A·A)′ = A′, which gives us inversion from a single NAND whose inputs are tied together.

NOT Using NAND (1 gate)

Tie both inputs of a NAND together: A′ = (A·A)′.

AND Using NAND (2 gates)

A NAND already computes (A·B)′, so inverting its output recovers AND: A·B = ((A NAND B) NAND (A NAND B)). One NAND produces the NAND term, a second NAND (acting as a NOT) inverts it.

OR Using NAND (3 gates)

By De Morgan’s theorem, A + B = (A′·B′)′ = A′ NAND B′. Invert each input with a NAND, then NAND the results: (A NAND A) NAND (B NAND B).

XOR Using NAND (4 gates)

The classic four-NAND XOR is elegant. Let C = A NAND B. Then form A NAND C and B NAND C, and NAND those two together. Algebraically the output is A·B′ + A′·B = A ⊕ B.

XNOR Using NAND (5 gates)

XNOR is the complement of XOR, so take the four-NAND XOR and add one more NAND as an inverter on its output: A XNOR B = (A ⊕ B)′. Total: 5 NAND gates.

Building Every Gate Using Only NOR

The NOR constructions mirror the NAND ones under duality: swap the roles of AND and OR, and swap 0 and 1. The core identity here is A NOR A = (A+A)′ = A′.

NOT Using NOR (1 gate)

Tie both inputs together: A′ = (A+A)′.

OR Using NOR (2 gates)

NOR gives (A+B)′, so invert it to get OR: A + B = (A NOR B) NOR (A NOR B).

AND Using NOR (3 gates)

By De Morgan’s theorem, A·B = (A′ + B′)′ = A′ NOR B′. Invert each input, then NOR the results: (A NOR A) NOR (B NOR B).

XNOR Using NOR (4 gates)

The dual of the four-NAND XOR produces XNOR directly. Let C = A NOR B. Form A NOR C and B NOR C, then NOR them. The result is A·B + A′·B′ = A XNOR B.

XOR Using NOR (5 gates)

XOR is the complement of XNOR, so take the four-NOR XNOR and add one more NOR as an inverter on its output: A ⊕ B = (A XNOR B)′. Total: 5 NOR gates.

Gate-Count Summary

The table below collects the minimum single-type gate counts used in the constructions above. Notice the neat symmetry: whatever is cheap in NAND (AND, 2 gates) is expensive in NOR (AND, 3 gates), and vice versa, because AND and OR swap roles under duality.

Why Universality Matters in CMOS and ASIC Standard-Cell Design

Universal gates are not just a textbook curiosity — they shape how real silicon is built. In CMOS, a gate is made from a pull-up network of PMOS transistors and a pull-down network of NMOS transistors. Because of how these networks conduct, naturally inverting gates (NAND, NOR, inverters) are the efficient primitives. A two-input NAND or NOR needs only four transistors, while a non-inverting two-input AND or OR is physically a NAND/NOR followed by an inverter — six transistors. In other words, CMOS wants to produce the complemented functions, which is exactly what makes NAND and NOR universal.

Several practical consequences follow:

• Standard-cell libraries are dominated by NAND, NOR and inverter variants in many drive strengths, because synthesis tools can map any logic onto them.
• Logic synthesis and technology mapping decompose arbitrary RTL into a network that is then covered by available cells; having a functionally complete primitive guarantees any design is realizable.
• Area, power and timing all benefit from fewer transistors and fewer stages, so tools prefer the inverting forms and push bubbles (inversions) around using De Morgan equivalences.
• Electrical characteristics differ: NAND gates tend to be preferred in many libraries because series NMOS (which conduct well) sit in the pull-down network, whereas NOR gates stack PMOS in series in the pull-up network, and PMOS is typically weaker — influencing sizing and speed.

Understanding universality therefore connects Boolean algebra directly to transistor-level layout and to the way automated flows build modern chips. When you see a gate-level netlist full of NAND and NOR cells, you are looking at this principle in action. If you want to go deeper into how these cells become transistors on silicon, the companion topic of the stick diagram in VLSI layout design is a natural next step, and reviewing how gates compose into larger blocks in a combinational circuit reinforces the bigger picture.

Learn CMOS and Standard-Cell Design Hands-On

If you want to master how universal gates translate into real transistor-level and ASIC design — from CMOS structures to standard-cell libraries and physical layout — explore the ASIC Physical Design course at ChipXpert, where these concepts are taught with practical, industry-aligned flows.

Frequently Asked Questions

What is a universal gate?

A universal gate is a logic gate that can implement any other Boolean function using only copies of itself. NAND and NOR are the two universal gates because each is functionally complete — it combines a basic operation (AND or OR) with inversion, which together can express every truth table.

Why are NAND and NOR considered universal gates?

Because the set {AND, OR, NOT} is functionally complete, and both NAND and NOR can individually generate all three. Tying a NAND’s (or NOR’s) inputs together produces NOT, and De Morgan’s theorem lets you build AND and OR from the inverting gate. From NOT, AND and OR, every other function — including XOR and XNOR — can be derived.

How many NAND gates are needed to make an XOR gate?

A standard XOR can be built from four NAND gates. If you first compute C = A NAND B, then A NAND C and B NAND C, and finally NAND those two results, the output is A ⊕ B. Adding one more NAND as an inverter turns it into an XNOR, for a total of five gates.

Is a NAND gate or a NOR gate better for CMOS design?

Both are universal, but many CMOS libraries favor NAND gates. In a NAND, the series transistors sit in the NMOS pull-down network, and NMOS conducts more strongly than PMOS; a NOR stacks PMOS in series in the pull-up network, which is typically slower for the same size. The final choice depends on the logic function, timing targets and the specific standard-cell library.

What does "universal gates logic" mean in digital electronics?

"Universal gates logic" refers to designing and analyzing circuits using only NAND or only NOR gates. Because these gates are functionally complete, entire logic systems — adders, multiplexers, flip-flops and more — can be expressed with a single gate type, which simplifies fabrication and is why they are central to real integrated-circuit design.