Sequential Circuits: Types and Examples

Sequential circuits are the branch of digital logic in which the output depends not only on the present inputs but also on the past history of inputs, which is held as stored state. This single property — memory — separates sequential logic from the purely input-driven world of combinational logic and makes it the foundation of registers, counters, finite state machines, and ultimately every processor and controller ever built. This reference article explains how a sequential circuit works, how it differs from combinational logic, the role of clocking and state, and the core building blocks: latches, flip-flops, registers, counters, and shift registers (including the serial in serial out register).

What Is a Sequential Circuit?

A sequential circuit is a logic network whose output is a function of both its current inputs and its current internal state. That state is stored in memory elements, and the stored value is fed back into the combinational logic that computes the next state. Because of this feedback loop, the same input applied at two different moments can produce two different outputs, depending on what the circuit “remembers.”

Formally, a sequential circuit can be described by two functions: a next-state function that computes the state to be stored next, and an output function that produces the outputs. When the output depends only on the current state, the machine is called a Moore machine; when the output depends on both the current state and the current inputs, it is a Mealy machine.

Combinational vs Sequential Circuits

The clearest way to understand sequential logic is to contrast it with combinational logic. A combinational circuit — such as an adder, a multiplexer, or a decoder — produces outputs that are an immediate function of the present inputs only, with no memory and no feedback. A sequential circuit adds storage and feedback. The comparison below summarizes the differences.

If you want a deeper refresher on the input-driven side of this comparison, see our companion article on what a combinational circuit is and how it works. A practical sequential design almost always combines both styles: blocks of combinational logic compute next-state and output values, while flip-flops hold the state between updates.

Synchronous vs Asynchronous Sequential Circuits

Sequential circuits are grouped by when their state is allowed to change.

Synchronous Sequential Circuits

In a synchronous circuit, every memory element updates in step with a common timing signal called the clock. State changes occur only at defined clock events — typically the rising or falling edge. Because all flip-flops sample together, timing is predictable and the circuit is far easier to analyze and verify. The overwhelming majority of modern digital systems are synchronous.

Asynchronous Sequential Circuits

In an asynchronous circuit, state can change as soon as an input changes, without waiting for a clock. These circuits can be faster and are used in specific places (such as simple latches and handshake logic), but they are prone to timing hazards and race conditions, making them harder to design correctly.

Clocking and State

The clock is a periodic signal that paces a synchronous circuit. Each clock cycle has a period (seconds) and a frequency (the reciprocal, in hertz). Memory elements respond to the clock in one of two ways:

• Level-sensitive elements (latches) are transparent while the clock is at an active level and hold their value otherwise.
• Edge-triggered elements (flip-flops) sample their input only at the instant of a clock transition — the rising edge (0→1) or falling edge (1→0).

Two timing constraints must be met for reliable operation. The setup time is the interval before the active clock edge during which the data input must be stable; the hold time is the interval after the edge during which it must remain stable. Violating either can drive the device into a metastable condition where its output is briefly undefined. The state of a circuit is simply the collection of values currently stored in all its flip-flops; an n-flip-flop circuit can represent up to 2ⁿ distinct states.

Building Blocks of Sequential Circuits

Latches

A latch is the simplest memory element: a level-sensitive bistable device. The classic SR (Set-Reset) latch built from two cross-coupled NOR gates has inputs S and R and outputs Q and Q′. Its behavior is summarized below, where Q denotes the current (held) output.

The S = R = 1 combination is forbidden for the NOR SR latch because it forces both outputs to 0, breaking the complementary Q/Q′ relationship and producing an unpredictable state when the inputs return to 0.

A D (data) latch removes the forbidden state by deriving R from the complement of S. When its enable line is active, Q simply follows D; when enable is inactive, the latch holds its last value.

Flip-Flops

A flip-flop is an edge-triggered memory element. Unlike a transparent latch, it changes state only at a clock edge, which makes it the workhorse of synchronous design. The four standard types are D, JK, T, and SR.

The D flip-flop captures the value of D at the active clock edge and holds it until the next edge. Its characteristic equation is simply Q_next = D.

The JK flip-flop is the most versatile: it resolves the SR forbidden state by toggling when both inputs are high. Its characteristic equation is Q_next = J·Q′ + K′·Q.

The T (toggle) flip-flop flips its output on every active edge when T = 1 and holds when T = 0. Its characteristic equation is Q_next = T ⊕ Q, which is why T flip-flops are natural building blocks for counters.

For a detailed, edge-by-edge treatment of each type — including excitation tables and conversions between them — see our dedicated guide to flip-flops and RTL design. In practice, the edge-triggered D flip-flop dominates real chips because it maps cleanly onto register-transfer-level descriptions written in Verilog or SystemVerilog.

Registers

A register is a group of flip-flops that share a common clock and store a multi-bit word. An n-bit register is built from n D flip-flops and holds an n-bit value that is updated together on each clock edge. Registers are everywhere in a datapath: they hold operands, accumulate results, and pipeline data between stages. A register with a parallel load can capture all n bits simultaneously, which is the basis for parallel-in parallel-out (PIPO) storage.

Counters

A counter is a sequential circuit that advances through a fixed sequence of states on successive clock edges. Counters fall into two families:

• Asynchronous (ripple) counters, in which each flip-flop is clocked by the output of the previous stage. They are simple but accumulate propagation delay down the chain.
• Synchronous counters, in which all flip-flops share the same clock and change together, eliminating ripple delay at the cost of extra combinational logic.

A modulo-N counter cycles through N states before repeating; a 4-bit binary counter, for example, counts from 0000 to 1111 (modulo-16) and then rolls over. Counters are used for frequency division, event counting, address generation, and timing.

Shift Registers

A shift register is a cascade of flip-flops in which the stored bits move one position along the chain on each clock edge. Shift registers are classified by how data enters and leaves:

• Serial In Serial Out (SISO) — one bit enters at a time and one bit leaves at a time.
• Serial In Parallel Out (SIPO) — bits are shifted in one at a time, then read out all at once.
• Parallel In Serial Out (PISO) — a full word is loaded at once, then shifted out one bit at a time.
• Parallel In Parallel Out (PIPO) — a word is loaded and read in parallel.

The serial in serial out register is the most basic form. Consider a 4-bit SISO register made of four D flip-flops D₀–D₃, where the output of each stage feeds the input of the next. If the register starts cleared and the serial input stream is 1, 0, 1, 1 (applied on four successive clock edges), the stored contents evolve as shown below.

After four clock edges the first bit that entered (a 1) appears at the serial output, demonstrating the n-cycle delay that an n-stage SISO register introduces. SISO registers are used for serial data delay, serial-to-serial buffering, and as the backbone of serial communication links.

How the Pieces Fit Together

A complete synchronous sequential system is organized as a loop. State flip-flops hold the current state; a block of combinational next-state logic reads the current state and the inputs to compute the value that will be stored on the next clock edge; and a block of output logic produces the outputs. The clock defines exactly when the computed next state replaces the current state. This structure — the classic finite state machine — is how controllers, protocol engines, and sequencers are specified and implemented. In digital design practice, engineers describe this behavior at the register-transfer level and let synthesis tools map it onto flip-flops and gates. If you are comparing hardware description languages for this work, our overview of Verilog vs SystemVerilog is a useful next read.

Learn Sequential Design Hands-On with ChipXpert

If you want to move from understanding these concepts to designing and verifying real sequential logic — flip-flops, counters, shift registers, and complete finite state machines in RTL — the ChipXpert Advanced RTL Design course walks you through synchronous design methodology, timing, and FSM coding with practical lab exercises.

Frequently Asked Questions

What is the difference between a combinational and a sequential circuit?

A combinational circuit produces outputs that depend only on its present inputs and has no memory. A sequential circuit has memory elements and feedback, so its output depends on both the present inputs and the stored past state. Counters, registers, and finite state machines are sequential; adders and multiplexers are combinational.

What is the difference between a latch and a flip-flop?

A latch is level-sensitive: it is transparent and passes data through whenever its enable line is at the active level. A flip-flop is edge-triggered: it samples its input and changes state only at a clock transition (rising or falling edge). Flip-flops are preferred in synchronous designs because their predictable timing makes circuits easier to analyze.

What is a serial in serial out (SISO) shift register?

A serial in serial out register is a chain of flip-flops where a single bit is shifted in on each clock edge and a single bit is shifted out at the far end. An n-stage SISO register delays the serial data stream by n clock cycles, which makes it useful for serial buffering and timing delay.

Why is a clock needed in a sequential circuit?

In a synchronous sequential circuit, the clock defines the exact moments at which all memory elements update together. This coordinated timing prevents race conditions, makes setup and hold constraints meaningful, and lets designers reason about one state transition per clock cycle. Asynchronous circuits can operate without a global clock but are much harder to design reliably.

What are the main types of sequential circuits?

They are broadly divided into synchronous circuits, which update on a common clock, and asynchronous circuits, which respond directly to input changes. Common building blocks include latches, flip-flops (D, JK, T, SR), registers, counters, and shift registers, which combine to form finite state machines.