Shift Registers: SISO, SIPO, PISO, PIPO

A shift register is a sequential logic circuit built from a cascade of flip-flops that stores and moves binary data one bit at a time on each clock edge. It is one of the most widely used building blocks in digital systems, sitting at the heart of operations such as serial-to-parallel conversion, data buffering, timing delays, and arithmetic shifting. This reference explains the four fundamental configurations defined by how data enters and leaves the register — SISO (serial-in serial-out), SIPO (serial-in parallel-out), PISO (parallel-in serial-out), and PIPO (parallel-in parallel-out) — before covering bidirectional and universal shift registers, real-world applications, and a short SISO Verilog model.

What Is a Shift Register?

Each stage of a shift register is a single flip-flop (usually a D-type for clarity, though JK, T, or SR flip-flops can be adapted). The output of one flip-flop feeds the input of the next, forming a chain. All flip-flops share a common clock, so on every active clock edge the stored pattern advances exactly one position through the chain. An n-bit register needs n flip-flops and can hold n bits. Because the state of the circuit depends on past inputs as well as present ones, a shift register is a classic example of a sequential circuit.

The two defining questions for any shift register are: how does data get in (serially, one bit per clock, or in parallel, all bits at once) and how does data come out (serially or in parallel)? The four combinations of these choices give the four classic types.

SISO — Serial-In Serial-Out

In a serial in serial out register, data enters one bit at a time through a single serial input and is read out one bit at a time from the final flip-flop. There is no access to the intermediate stages. A SISO register is therefore the purest form of a digital delay line: a bit applied at the input appears at the output after exactly n clock pulses in an n-bit register.

Diagram Description

Picture four D flip-flops labelled Q0, Q1, Q2, Q3 drawn left to right. The serial data line connects to the D input of Q0. The Q output of Q0 drives the D input of Q1, Q1 drives Q2, and Q2 drives Q3. A single clock line runs underneath to the clock input of all four flip-flops. Only the Q output of Q3 is brought out as the serial output pin; Q0, Q1, and Q2 outputs stay internal.

Operation Table

The table below shifts the serial sequence 1, 0, 1, 1 (applied on successive clocks) into a 4-bit SISO register that starts cleared. The serial output is the value of Q3.

Notice that the first bit (1) does not reach Q3 until the fourth clock — the n-clock latency that makes SISO useful as a delay element.

SIPO — Serial-In Parallel-Out

A SIPO register accepts data serially, one bit per clock, but exposes the output of every flip-flop simultaneously as parallel output lines. After n clock pulses an n-bit serial stream is fully loaded and can be read out in one step across all n pins. This is precisely the function needed to turn a serial communication line into a parallel word.

Diagram Description

The internal chain is identical to the SISO register — serial input into Q0, each Q cascading to the next D input, a shared clock — but now Q0, Q1, Q2, and Q3 are each routed to their own output pin. Nothing changes inside; only the output tapping differs.

Operation Table

Loading the same serial sequence 1, 0, 1, 1 into a cleared 4-bit SIPO register:

After clock 4 the parallel output (Q0 Q1 Q2 Q3) reads 1 1 0 1 — the full word is available at once. The 74HC164 is a common commercial SIPO device.

PISO — Parallel-In Serial-Out

The parallel in serial out register performs the inverse of SIPO. All data bits are loaded simultaneously into the flip-flops through parallel inputs during a load operation, then clocked out one bit at a time through a single serial output during a shift operation. A PISO shift register therefore needs a mode-control signal, often called LOAD/SHIFT (or SHIFT/LOAD), to select between the two behaviours.

Diagram Description

Each flip-flop has a two-input multiplexer in front of its D input. When the control line selects load, each multiplexer passes that stage’s parallel data bit (P0, P1, P2, P3) directly into the flip-flop. When the control line selects shift, each multiplexer instead passes the previous stage’s Q output, reconnecting the flip-flops into the familiar serial chain. The serial output is taken from the last flip-flop, Q3.

Operation Table

Here the parallel word P = 1011 (P0=1, P1=0, P2=1, P3=1) is loaded, then shifted out. With Load = 1 the word is captured; with Load = 0 the register shifts right and a 0 enters at Q0.

Reading the Serial Out column across clocks 1 to 4 gives the sequence 1, 1, 0, 1 — the stored word emerging one bit per clock, most-significant stage (Q3) first. The 74HC165 is a well-known PISO part used to read banks of switches over a single serial line.

PIPO — Parallel-In Parallel-Out

A PIPO register loads all bits in parallel and reads all bits out in parallel. On a single clock edge, every parallel input is captured into its flip-flop, and every output is immediately available. There is no shifting involved in the basic PIPO configuration — it functions as a simple n-bit storage register or data latch, holding a word for one or more clock cycles.

Diagram Description

Four D flip-flops sit side by side with no interconnection between them. Each parallel input P0–P3 goes straight to the D input of its own flip-flop, and each Q0–Q3 output is brought out directly. A common clock latches all four at the same instant.

Operation Table

The output tracks the parallel input captured on each clock edge, with a latency of one clock cycle. PIPO registers are the standard way to build pipeline stages and hold intermediate results between logic blocks.

Comparison of the Four Types

Bidirectional Shift Registers

The registers above all shift in one direction (conventionally right, from Q0 toward Q3). A bidirectional shift register can shift either right or left under control of a direction signal. Each flip-flop input is driven by a multiplexer that selects between the stage to its left (for a right shift) and the stage to its right (for a left shift), plus serial inputs at each end. A single RIGHT/LEFT control line chooses the direction.

Bidirectional shifting is essential for arithmetic: shifting a binary number left by one position multiplies it by two, while shifting right divides it by two (with care taken over sign extension for signed numbers).

Universal Shift Registers

A universal shift register combines all of the above capabilities in one device. It can load data in parallel, shift right, shift left, or hold its current value, selected by two mode-control bits S1 and S0. Each flip-flop is fed by a 4-to-1 multiplexer whose select lines are S1 and S0. The classic example is the 74LS194 4-bit universal shift register.

Because it supports every input/output mode and both shift directions, a universal shift register can be configured as any of SISO, SIPO, PISO, or PIPO, making it a flexible core for data paths and controllers — including the kind of datapath elements you design when building a finite state machine and its surrounding logic.

Applications of Shift Registers

• Serial-to-parallel and parallel-to-serial conversion: SIPO and PISO registers form the backbone of serial communication interfaces such as SPI and UART, converting between the single-wire serial streams used on buses and the parallel words used inside a processor.
• Data delay: A SISO register delays a signal by a fixed number of clock cycles, useful for aligning data paths and compensating for pipeline latency.
• Temporary storage and buffering: PIPO registers hold words between stages of a computation.
• Arithmetic shifting: Left and right shifts implement multiplication and division by powers of two in ALUs and multipliers.
• Ring and Johnson counters: Feeding the output of a shift register back to its input produces compact counters and sequence generators.
• Pseudo-random sequence generation: A linear-feedback shift register (LFSR) uses XOR feedback taps to produce long pseudo-random bit sequences for test patterns, scramblers, and CRC calculation.
• I/O expansion: Driving many LEDs or reading many switches through a few microcontroller pins relies on SIPO and PISO devices respectively.

A Short SISO Shift Register in Verilog

The following synthesizable model describes a 4-bit serial-in serial-out register. On every rising clock edge the serial input bit shifts into the low end and each stored bit moves up one position; the serial output is the top bit of the register. If you are comparing hardware description languages for this kind of RTL, our note on Verilog vs SystemVerilog is a useful companion.

module siso_shift_reg (
    input  wire clk,
    input  wire rst_n,      // active-low synchronous reset
    input  wire serial_in,
    output wire serial_out
);
    reg [3:0] shreg;

    always @(posedge clk) begin
        if (!rst_n)
            shreg <= 4'b0000;
        else
            shreg <= {shreg[2:0], serial_in};  // shift left; new bit enters LSB
    end

    assign serial_out = shreg[3];   // oldest bit leaves from the MSB
end
endmodule

The concatenation {shreg[2:0], serial_in} is the whole shift operation: the existing bits 0–2 move up to positions 1–3, and the new serial bit drops into position 0. A bit applied to serial_in appears at serial_out four clocks later, matching the delay-line behaviour described earlier.

Learn RTL Design Hands-On

Shift registers are one of the first sequential building blocks every digital designer masters, and they lead directly into counters, FSMs, and full datapath design. If you want structured, project-driven training in Verilog and RTL design — from flip-flops through complete synthesizable blocks — explore the ChipXpert Advanced RTL Design course (online and offline).

Frequently Asked Questions

What is a serial in serial out (SISO) register used for?

A serial in serial out register loads data one bit per clock through a single input and reads it out one bit per clock from the last flip-flop. Its main use is as a digital delay line or serial buffer: an n-bit SISO register delays the input stream by exactly n clock cycles, which helps align signals across pipeline stages.

What is the difference between SIPO and PISO shift registers?

A SIPO (serial-in parallel-out) register takes data in serially and presents all bits in parallel at once, performing serial-to-parallel conversion. A PISO shift register (parallel-in serial-out) does the opposite: it loads all bits in parallel in a single step, then clocks them out one bit at a time through a single serial output. SIPO is used to receive serial data into a parallel word, while PISO is used to transmit a parallel word over a serial line.

How does a parallel in serial out register select between load and shift?

A parallel in serial out register uses a mode-control line, commonly called LOAD/SHIFT. When load is asserted, a multiplexer in front of each flip-flop passes the parallel data bits straight into the register. When shift is asserted, the multiplexers reconnect the flip-flops as a serial chain so the stored word moves out one bit per clock through the serial output.

What is a universal shift register?

A universal shift register can perform parallel load, shift right, shift left, and hold, all selected by two mode-control bits. Because it supports every input and output mode, it can be configured to behave as a SISO, SIPO, PISO, or PIPO register. The 74LS194 is a common 4-bit universal shift register.

Why does shifting a binary number left or right perform multiplication or division?

Shifting a binary value left by one position appends a zero at the least-significant end and moves every bit to a higher weight, which doubles the value — the same as multiplying by two. Shifting right moves each bit to a lower weight, dividing by two. Bidirectional and universal shift registers provide this directly, which is why they appear inside ALUs and multiplier circuits.

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