Full Adder and Half Adder: Circuit and Truth Table

Binary addition is the foundation of every arithmetic operation a digital computer performs, and the circuits that carry it out are the half adder and the full adder. These two combinational building blocks take binary digits as inputs and produce a sum bit and a carry bit. Understanding the half adder and full adder — their circuits, truth tables, Boolean expressions, and logic diagrams — is essential for anyone learning digital logic design, computer architecture, or RTL hardware design. This article walks through both circuits in detail, shows how a full adder is constructed from two half adders, and explains how adders cascade to form a ripple-carry adder capable of adding multi-bit numbers.

What Is a Half Adder?

A half adder is the simplest binary addition circuit. It adds two single-bit binary numbers, labelled A and B, and produces two outputs: a Sum bit (S) and a Carry bit (C). It is called a “half” adder because it cannot accept a carry input from a previous stage — it handles only two operands, which makes it incomplete for anything beyond the least significant bit of a larger addition.

When you add two bits, the possible results are 0, 1, or 2 (binary 10). The sum output represents the least significant bit of the result, and the carry output represents the overflow into the next column.

Half Adder Truth Table

The behaviour of the half adder is fully described by the following truth table half adder designers rely on:

Half Adder Boolean Expressions

Reading the output columns of the truth table reveals two familiar logic functions:

• Sum = A ⊕ B (the exclusive-OR, or XOR, of the two inputs)
• Carry = A · B (the logical AND of the two inputs)

The sum column is 1 only when exactly one input is 1, which is precisely the definition of XOR. The carry column is 1 only when both inputs are 1, which is the AND function.

Half Adder Circuit Diagram

The half adder circuit diagram therefore needs just two gates: one XOR gate to generate the sum and one AND gate to generate the carry. Both gates share the same two inputs. In text form the structure looks like this:

A ----+----------[ XOR ]---- Sum
      |        /
      |   +---/
B --+-|---+
    | |
    | +------[ AND ]-------- Carry
    |       /
    +------/

Both A and B feed the XOR gate (producing Sum) and the AND gate (producing Carry) in parallel. Because there is no feedback and the outputs depend only on the present inputs, the half adder is a purely combinational circuit.

What Is a Full Adder?

A full adder solves the limitation of the half adder by accepting three inputs: the two operand bits A and B, plus a carry-in bit (Cin) from the previous, less significant stage. It produces a Sum output (S) and a carry-out output (Cout). This third input is what allows full adders to be chained together to add binary numbers of any width.

Because three one-bit inputs can represent sums from 0 up to 3 (binary 11), the two output bits, Sum and carry-out, together express the full result of adding three bits.

Full Adder Truth Table

With three inputs there are eight input combinations. The complete full adder logic table is:

A useful sanity check: the Sum output is 1 whenever an odd number of the three inputs is 1, and the carry-out is 1 whenever two or more of the inputs are 1 (a majority function).

Full Adder Boolean Expressions

Simplifying the truth table gives compact expressions for both outputs:

• Sum = A ⊕ B ⊕ Cin
• Cout = (A · B) + (Cin · (A ⊕ B))

The carry-out expression can also be written in the symmetric sum-of-products form that drops out of the truth table directly:

• Cout = A·B + B·Cin + A·Cin

Both carry-out forms are logically equivalent. The first form is preferred when building a full adder from half adders, because the (A ⊕ B) term is already available from the first half adder, as shown below.

Building a Full Adder from Two Half Adders

One of the most instructive results in digital logic is that a full adder can be assembled from two half adders plus a single OR gate. This demonstrates how larger functions are composed from smaller reusable blocks — a principle that extends all the way up to processor design.

1. First half adder: It adds A and B. Its sum output is the intermediate value S1 = A ⊕ B, and its carry output is C1 = A · B.
2. Second half adder: It adds the intermediate sum S1 to the carry-in Cin. Its sum output is the final sum S = S1 ⊕ Cin = A ⊕ B ⊕ Cin, and its carry output is C2 = S1 · Cin.
3. OR gate: The final carry-out is produced by OR-ing the two intermediate carries: Cout = C1 + C2 = (A · B) + ((A ⊕ B) · Cin), which matches the full adder carry-out expression exactly.

Full Adder Circuit Diagram (from Half Adders)

The full adder circuit built this way can be described textually as follows:

            +----------------+
A ---+----->|  Half Adder 1  |-- S1 (A XOR B) --+----------------+
B ---+----->|                |-- C1 (A AND B) -+|                |
            +----------------+                 ||  Half Adder 2  |-- S (Sum)
                                               +|                |-- C2
Cin ------------------------------------------->|                |
                                                +----------------+
                                                     |
                               C1 ---+               |
                                     +---[ OR ]------+--- Cout
                               C2 -------/

Here Half Adder 1 processes A and B, Half Adder 2 processes the partial sum with Cin, and the OR gate combines the two carries into the final carry-out. If you prefer the gate-level view, a full adder uses two XOR gates, two AND gates, and one OR gate.

The Ripple-Carry Adder

A single full adder handles one bit position. To add multi-bit binary numbers — say two 4-bit numbers A3A2A1A0 and B3B2B1B0 — you cascade four full adders into a ripple-carry adder. Each full adder adds one pair of bits along with the carry from the stage to its right.

• The least significant stage (bit 0) can be a full adder with its carry-in tied to 0, or simply a half adder.
• The carry-out of each stage becomes the carry-in of the next, more significant stage.
• The carry-out of the most significant stage indicates an overflow for unsigned addition.

The name “ripple-carry” comes from the way the carry signal propagates, or ripples, from the least significant bit to the most significant bit. The circuit is simple and area-efficient, but its main drawback is speed: the final sum is not valid until the carry has rippled through every stage. For an n-bit adder, the worst-case delay grows linearly with n. This is why faster architectures such as carry-look-ahead adders, carry-select adders, and carry-save adders were developed — they reduce carry-propagation delay at the cost of additional logic.

Half Adder vs Full Adder: Key Differences

Why Adders Matter in VLSI Design

Adders are everywhere in digital hardware. They form the heart of the arithmetic logic unit (ALU) in every processor, they appear inside multipliers and digital signal processing blocks, and they are a standard exercise when learning hardware description languages. Writing a full adder and a ripple-carry adder in Verilog is often one of the first RTL coding tasks, and understanding the underlying gate-level structure helps you reason about timing, area, and power trade-offs when you later synthesise and place-and-route a design. If you are comparing hardware description languages for this kind of modelling, our guide on Verilog vs SystemVerilog is a helpful next read.

If you want to go deeper into designing combinational and sequential circuits, writing clean synthesisable RTL, and building arithmetic units like adders and ALUs from first principles, explore the ChipXpert Advanced RTL Design course, where these fundamentals are taught alongside hands-on hardware design projects.

Frequently Asked Questions

What is the main difference between a half adder and a full adder?

The key difference is the carry-in. A half adder adds only two bits (A and B) and has no way to accept a carry from a previous stage. A full adder adds three bits (A, B, and a carry-in), which lets it be chained with other full adders to add multi-bit binary numbers. Both produce a sum bit and a carry bit.

What is the truth table of a half adder?

For inputs A and B, the half adder produces Sum = A XOR B and Carry = A AND B. The sum is 1 only when exactly one input is 1 (01 and 10 give Sum = 1), and the carry is 1 only when both inputs are 1 (11 gives Carry = 1). All other combinations give Carry = 0.

What are the Boolean expressions for a full adder?

The full adder sum is Sum = A ⊕ B ⊕ Cin, and the carry-out is Cout = A·B + B·Cin + A·Cin, which can equivalently be written as Cout = (A·B) + ((A ⊕ B)·Cin). The sum is 1 for an odd number of 1 inputs, and the carry-out is 1 when at least two inputs are 1.

Can a full adder be made from two half adders?

Yes. The first half adder adds A and B, producing a partial sum and a carry. The second half adder adds that partial sum to the carry-in, producing the final sum and a second carry. An OR gate then combines the two carry signals to produce the full adder’s carry-out.

What is a ripple-carry adder?

A ripple-carry adder is a chain of full adders used to add multi-bit binary numbers. The carry-out of each stage feeds the carry-in of the next more significant stage, so the carry “ripples” from the least significant bit to the most significant bit. It is simple but relatively slow, because the final result is valid only after the carry has propagated through every stage.

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