Demultiplexer (DEMUX): Truth Table and Working

A demultiplexer (often shortened to DEMUX) is a combinational logic circuit that takes a single input data line and routes it to one of several output lines. The particular output chosen is decided by a set of select (or address) lines. In short, a demultiplexer performs the opposite function of a multiplexer: where a multiplexer funnels many inputs into one line, a demultiplexer fans one input out to many lines. For this reason the DEMUX is frequently described as a data distributor.

A demultiplexer with n select lines can drive up to 2ⁿ output lines. So a 1-line select controls a 1-to-2 DEMUX, 2 select lines control a 1-to-4 DEMUX, and 3 select lines control a 1-to-8 DEMUX. Understanding these three standard sizes gives you everything needed to reason about any larger demultiplexer.

What a Demultiplexer Does

Picture a single wire carrying a stream of data bits. A demultiplexer acts like a controllable switch that connects that one wire to exactly one of many destination wires at any instant. The select lines behave like the dial on that switch, picking which destination is active. Every output that is not selected is held at logic 0, while the selected output faithfully copies the value present on the data input.

This behaviour makes the DEMUX extremely useful whenever a shared resource — a serial communication channel, a processor data bus, or a single sensor line — must deliver its information to one of several targets at different times.

1-to-2 Demultiplexer

The simplest demultiplexer has one data input (D), one select line (S), and two outputs (Y0 and Y1). The block diagram shows a single input entering the left side, one select line entering from below, and two output lines leaving the right side. Internally it is built from two AND gates and one NOT gate (inverter): one AND gate combines D with the inverted select, the other combines D with the true select.

When S = 0, the data is routed to Y0 and Y1 stays at 0. When S = 1, the data is routed to Y1 and Y0 stays at 0.

The Boolean output expressions for the 1 to 2 demultiplexer are:

• Y0 = D · S'
• Y1 = D · S

1-to-4 Demultiplexer

A 1 to 4 demultiplexer routes one data input to one of four outputs (Y0–Y3) using two select lines, S1 and S0. The demultiplexer diagram for this circuit uses four three-input AND gates, each receiving the data input plus a unique combination of the true and complemented select signals. Two inverters generate the complemented select lines.

The two select bits form a binary address from 00 to 11, and that address picks which of the four outputs receives the data.

Here the entry D means the output follows the data input (it is 0 when D = 0 and 1 when D = 1), while every other output is forced to 0. The Boolean output expressions are:

• Y0 = D · S1' · S0'
• Y1 = D · S1' · S0
• Y2 = D · S1 · S0'
• Y3 = D · S1 · S0

1-to-8 Demultiplexer

A 1-to-8 demultiplexer extends the idea to eight outputs (Y0–Y7) controlled by three select lines, S2, S1, and S0. The demux logic diagram now contains eight four-input AND gates, each fed by the data line and one unique product of the three select variables. The three-bit address ranges from 000 to 111, selecting exactly one of the eight outputs.

In every row, only the listed output follows D while all seven remaining outputs are 0. The general Boolean form is Y_k = D · m_k, where m_k is the minterm of the select lines corresponding to output number k. For example:

• Y0 = D · S2' · S1' · S0'
• Y5 = D · S2 · S1' · S0
• Y7 = D · S2 · S1 · S0

Relationship Between a Demultiplexer and a Decoder

A demultiplexer is structurally almost identical to a decoder. A decoder with an enable input is, in fact, the same hardware as a demultiplexer. In a decoder, the select-like inputs are the address being decoded and the enable line activates exactly one output. In a demultiplexer, those address inputs become the select lines and the enable line becomes the data input.

Concretely, if you take a 3-to-8 decoder and feed your data signal into its enable pin, the three address pins act as the DEMUX select lines and the eight decoder outputs become the eight DEMUX outputs. This is why many catalog chips are labelled “decoder/demultiplexer” — the single device serves both roles depending on how you wire it. If you want to go deeper into this duality, our guide on the encoder and decoder circuits walks through the enable-driven conversion in detail.

DEMUX vs MUX: A Comparison

The multiplexer and demultiplexer are complementary building blocks, often used together at opposite ends of a data link. The table below summarises the key differences.

A classic pairing uses a MUX to compress several parallel signals onto one wire for transmission, and a matching DEMUX at the far end to spread them back out. If you are new to the selector side of this pair, our explainer on the 4-to-1 multiplexer is a helpful companion to this page.

Applications of Demultiplexers

Because a DEMUX can steer data to a chosen destination, it appears across many digital systems:

• Data distribution: routing one data source to several subsystems, memory banks, or peripherals one at a time.
• Serial-to-parallel conversion: combined with a counter driving the select lines, a demultiplexer can take a serial bit stream and distribute successive bits onto separate parallel lines.
• Communication systems: at the receiving end of a time-division multiplexed channel, separating the recombined data back into its original channels.
• Memory and I/O addressing: acting as an address decoder (its decoder twin) to enable one memory chip or output device among many.
• Clock and control steering: directing a clock or enable pulse to a selected functional block.

The serial-to-parallel use case shows how combinational demultiplexers interact with clocked, sequential building blocks. If you want to understand the storage elements that feed such designs, see our introductions to sequential circuits and the fundamental storage cell in our JK flip-flop article.

Designing with Demultiplexers in RTL

In modern chip design, engineers rarely wire DEMUX gates by hand. Instead they describe the routing behaviour in a hardware description language such as Verilog or VHDL, where a demultiplexer maps naturally onto a case statement or an indexed assignment driven by the select bits. The synthesis tool then builds the AND/NOT structure automatically. Learning to express multiplexers, demultiplexers, decoders, and counters cleanly in RTL is a core skill for any front-end design engineer.

If you want to master combinational and sequential circuit design all the way to synthesizable RTL, explore our VLSI Advanced RTL Design course, where demultiplexers, counters, and finite state machines are taught with hands-on coding labs.

Frequently Asked Questions

What is a demultiplexer in simple terms?

A demultiplexer is a digital circuit that takes one data input and sends it to one of several outputs, with select lines deciding which output is active. It is the reverse of a multiplexer, so it is often called a data distributor.

How many select lines does a 1-to-8 demultiplexer need?

A 1-to-8 demultiplexer needs three select lines. In general, a demultiplexer with 2ⁿ outputs requires n select lines, so 8 outputs need 3 select lines (2³ = 8).

What is the difference between a demultiplexer and a decoder?

They use the same internal logic. A decoder with an enable input behaves exactly like a demultiplexer: the decoder's address inputs act as the select lines and its enable input acts as the data input. This is why many devices are sold as combined decoder/demultiplexer chips.

What are the Boolean expressions for a 1-to-4 demultiplexer?

With data input D and select lines S1 and S0, the four outputs are Y0 = D·S1'·S0', Y1 = D·S1'·S0, Y2 = D·S1·S0', and Y3 = D·S1·S0. Only the addressed output follows D; the others stay at 0.

Why is a demultiplexer used in serial-to-parallel conversion?

When its select lines are driven by a counter, a demultiplexer sends each successive serial bit to a different output line. After one full count cycle, the bits that arrived one after another on a single wire are available together on separate parallel lines.

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