Master-Slave Flip-Flop Explained

A master-slave flip-flop is a flip-flop built from two latches connected in series and clocked on opposite phases. This arrangement converts two level-sensitive latches into a single edge-triggered element, eliminating the “race-around” problem of a simple clocked JK flip-flop. It is the classic way edge triggering is implemented in real hardware. This guide explains the structure and operation.

Why a master-slave structure is needed

A level-triggered JK flip-flop with J = K = 1 toggles continuously while the clock is high — the output oscillates several times in one clock pulse. This race-around condition makes the final state unpredictable. The master-slave design fixes it by ensuring the output can change only once per clock cycle, at a single edge.

Structure

Two latches in series:

• Master latch — enabled when the clock is high. It samples the inputs.
• Slave latch — enabled when the clock is low (clock is inverted to the slave). It copies the master’s value to the output.

Because the two latches are never transparent at the same time, data captured by the master only reaches the output when the clock falls — making the whole circuit behave as a negative-edge-triggered flip-flop.

Operation step by step

1. Clock high: master follows the J/K (or D) inputs; slave holds, so the output is unchanged.
2. Clock falls: master locks its value; slave becomes transparent and passes that value to the output.
3. Clock low: master is isolated from the inputs, so no further change can propagate this cycle.

The result: exactly one output update per clock period, with no race-around.

Master-slave vs simple clocked flip-flop

Relationship to edge-triggered flip-flops

The master-slave topology is one way to achieve edge triggering; modern standard-cell flip-flops often use a slightly different edge-triggered structure, but the principle — two stages that are never simultaneously transparent — is the same. See latch vs flip-flop for the broader level-vs-edge distinction.

FAQs on the master-slave flip-flop

What is a master-slave flip-flop?

A flip-flop made of two latches in series clocked on opposite phases, so it behaves as a single edge-triggered element and updates its output only once per clock cycle.

How does it solve the race-around condition?

The master and slave latches are never transparent at the same time, so a JK input of 1,1 can toggle the stored value only once per clock period instead of oscillating while the clock is high.

Which edge does a master-slave flip-flop trigger on?

In the standard configuration (master enabled on clock high, slave on clock low) the output changes on the falling edge, making it negative-edge triggered. Inverting the clocking makes it positive-edge triggered.

How many latches are in a master-slave flip-flop?

Two — one master latch and one slave latch.

Learn sequential logic design in ChipXpert’s RTL Design course. Related: JK flip-flop, sequential circuits.